Reliability of High Speed Ultra Low Voltage Differential CMOS Logic  

作　　者：Omid Mirmotahari Yngvar Berg 

机构地区：[1]Nanoelectronics System Group, Department of Informatics, Universisty of Oslo, Oslo, Norway [2]Department of Micro- and Nanosystems Technology, Buskerud & Vestfold University College, Horten, Norway

出　　处：《Circuits and Systems》2015年第5期121-135,共15页电路与系统（英文）

摘　　要：In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.

关 键 词：CMOS DIFFERENTIAL FLOATING-GATE Semi-Floating-Gate KEEPER RECHARGE ULTRA Low Voltage High Speed Monte-Carlo CADENCE STM 90 nm 

分 类 号：R73[医药卫生—肿瘤]