Project supported by the National High Technology Research and Development Program of China(No.SQ2008AA01Z4473469)
A novel toggled flip-flop(TFF) divide-by-two circuit(DTC) and its optimization method based on a large-signal analysis approach are proposed.By reducing the output RC constant in tracking mode and making it large ...
supported by the National High Technology Research and Development Program of China(No.SQ2008AA01Z4473469).
A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump...