国家高技术研究发展计划(SQ2008AA01Z4473469)

作品数:2被引量:0H指数:0
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相关期刊:《Journal of Semiconductors》更多>>
相关主题:PLLMHZDYNAMICCMOS_TECHNOLOGYPHASE-LOCKED_LOOP更多>>
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Design and optimization of an ultra-wide frequency range CMOS divide-by-two circuit
《Journal of Semiconductors》2010年第11期122-126,共5页陆波 梅年松 陈虎 洪志良 
Project supported by the National High Technology Research and Development Program of China(No.SQ2008AA01Z4473469)
A novel toggled flip-flop(TFF) divide-by-two circuit(DTC) and its optimization method based on a large-signal analysis approach are proposed.By reducing the output RC constant in tracking mode and making it large ...
关键词:TFF DTC PLL ultra-wide frequency range optimization method in-band phase noise 
A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology
《Journal of Semiconductors》2010年第1期46-50,共5页陈虎 陆波 邵轲 夏玲琍 黄煜梅 洪志良 
supported by the National High Technology Research and Development Program of China(No.SQ2008AA01Z4473469).
A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump...
关键词:PLL in-band noise dynamic mismatch RMS jitter 
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