亚微米双层多晶硅自对准双极晶体管性能研究  

Research of the Performance of the Submicrometer Double Polysilicon Self-aligned Bipolar Transistors

作　　者：张志勇[1] 海潮和[1] 

机构地区：[1]中科院微电子中心,北京100029

出　　处：《电子与封装》2005年第9期29-33,共5页Electronics & Packaging

摘　　要：本文采用亚微米工艺和自对准技术制作了发射区宽度分别为0.8μm和0.4μm的两种双层多晶硅自对准双极晶体管。其中采用的是深沟和LOCOS两种隔离联合的隔离方法;EB间自对准是通过均匀的高质量的SiNx侧墙实现的,EB结击穿电压高达4.5V;窄的发射区使得发射极多晶硅在发射区窗口严重堆积,引起了双极晶体管的电流增益增大,同时也降低了管子的速度。工艺和器件模拟显示,发射极多晶硅采用原位掺杂技术,双极晶体管的性能得到了很大的改善。Two kinds of double polysilicon self-aligend bipolar transistors are fabricated by sub micrometer technology and self-aligned spacer. Deep trench isolation and LOCOS isolation are used at same time. The self-aligned between the emitter and base is achieved by a layer of high quality SiNx sidewall spacer whose width is 200nm, so we get the NPN transistor with high BVCDO as 4.5V. Because the emitter is very narrow, the layer of polysilicon on the emitter windows is plugged seriously. So the current gain is improved and the speed is lowed. We simulated the process and device of the in-situ doped DPSA bipolar through TSUPREM4 and MEDICI. The result shows the performance of the bipolar is improved greatly.

关 键 词：亚微米工艺 自对准技术 双层多晶硅 双极晶体管 原位掺杂 

分 类 号：TN32[电子电信—物理电子学]