一种新型低峰值功耗的BIST设计研究  

A New Design for Peak-power BIST

作　　者：刘建军[1] 刘伟[1] 康跃明[1] 

机构地区：[1]桂林电子科技大学计算机辅助测试教研室,广西桂林541004

出　　处：《电子与封装》2007年第9期4-7,33,共5页Electronics & Packaging

摘　　要：随着手持设备的兴起和芯片对晶片测试的要求越来越高,内建自测试的功耗问题引起了越来越多人的关注。文章对目前内建自测试的可测性设计技术进行了分析,并提出了折叠种子优化降低节点峰值功耗的模型,通过调整种子结构和测试向量的相关性的办法来避免过高的SoC测试峰值功耗。采取了屏蔽无效测试模式生成、提高应用测试向量之间的相关性以及并行加载向量等综合手段来控制测试应用,使得测试时测试向量的输入跳变显著降低,从而大幅度降低节点的峰值功耗。实验结果表明,该方案可以有效地避免BIST并行执行可能带来的过高峰值功耗。With the fast growing of portable-electronics and higher need of wafer test, power consumption problem of built-in self-test （ BIST ） has attracted more and more considerations. In this paper, we analyze the design for testability （ DFT ） of BIST and proposed the folding seed optimization reduces the node peak value power loss model, in this model foundation, proposed has avoided the high SoC test peak value power loss through the adjustment seed structure and the test vector relevant means. The scheme adopts some synthesis measures that deletes the void orredundancy testing patterns and increases the relativity of the test vectors and parallel loaded test vectors, so that the Peak -power consumption inside the circuit under testing is reduced enormously. The results of experiment show that this scheme can effectively avoid high peak-power during BIST concurrent execution.

关 键 词：内建自测试 可测性设计 低峰值功耗 片上系统 

分 类 号：TN407[电子电信—微电子学与固体电子学]