选择性BF_2^+离子注入对提高DRAM刷新时间的研究  

Improvement of DRAM Refresh Time by Selective Cell Lightly Doped Drain Bitline Contact BF_2^+ Implant

作　　者：彭坤[1,2,3] 王飚[1] 林大成[3] 吴萍[3] 外山弘毅 

机构地区：[1]昆明理工大学机电学院,昆明650093 [2]西南交通大学经济管理学院,成都610031 [3]中芯国际集成电路制造有限公司,天津300381 [4]富士通微电子株式会社FCRAM产品部

出　　处：《微细加工技术》2008年第5期1-4,15,共5页Microfabrication Technology

基　　金：国家自然科学基金资助项目(50371033);高等学校博士学科点专项科研基金资助项目(20040674009);中芯国际集成电路制造有限公司;日本富士通微电子株式会社企业资助

摘　　要：动态随机存储器(dynamic randomaccess memory,DRAM)电容器在存储高电位数据"1"时,将影响邻近记忆单元区晶体管栅极电场分布,从而导致漏电流增加,降低了刷新时间。研究提出针对位元线接触区、有选择性的浅掺杂漏极离子注入BF2+方案来改善刷新时间,模拟分析了其注入离子分布及电迁移,发现在位元线接触区硅基单侧浅表层形成了富硼离子注入区,且最大电迁移深度仅为60 nm,由此减少了对其它掺杂区的影响。电性测试结果表明,BF2+离子剂量与开启电压成正比,重复实验证明,该方案有良好的可再现性;分析结果表明,增加BF2+离子注入剂量能提高开启电压对制造偏差的容差能力;栅极关键尺寸在(90±15)nm波动范围内晶圆样品的NMOS电性测试结果表明,该离子注入法能保持与原有工艺的良好匹配性。进一步的分析结果指出,若开启电压升高,则刷新时间将会减少,若开启电压为0.8 V时,该离子注入方案能使刷新时间从180 ms提升到不小于300 ms,改良幅度达66.7%。模拟及实验分析结果表明,该离子注入方案能应用于深微米进程的研究与生产中。When the capacitors of the dynamic random access memory is storing signal ＂1＂ ,its higher voltage will affect the distribution of electric field of cell transistors which will increase the leakage current and degrade the refresh time. A solution has been proposed to improve the refresh time by only focused on the cell bitline contact area with cell lightly doped drain BF2^＋ implant （CLDD implant）. The memory cell was modeled using 90 nm NMOS transistors with CLDD implant, and B^＋ rich area on silicon surface was found at each sides of the bitline contact to substrate bottom by the simulated Boron distribution. The simulation result of electromigration （Era） distribution showed that the maximum depth of electromigration （Era） distribution was only about 60 nm, which was much lower than the baseline condition. CLDD implant had lower impact to other previous implanted area, so it would decrease the leakage current. The electronic test result showed that the threshold voltage was in direct proportion with the dosage of BF2^＋ implant, and series of experiments results were also proposed that CLDD implant solution was repeatable judged by the electronic test result. Data analysis result showed that higher dosage of CLDD implant would have larger device margin for the cell NMOS gate critical dimension （CD）. The effect of the cell NMOS gate criteria dimension was also studied at the range of 90 nm ± 15 nm. The transistor electronic test result showed that NMOS electronic parameter could match with original process when applied CLDD implant. It was pointed out that the refresh time of DRAM was inversely proportional to the cell NMOS threshold voltage. If the threshold voltage was O. 8 V,it was found that the refresh time had been increase from 180 ms to 300 ms, which had been improved 66.7%. The solution was also qualified to greatly improve the refresh time for the mass production of DRAM.

关 键 词：离子注入 动态随机存储器 刷新时间 漏电流 

分 类 号：TN304[电子电信—物理电子学]