一种新型D-RESURF埋栅SOI LDMOS  

A Novel D-RESURF SOI LDMOS with Embedded Gate

作　　者：廖红[1] 张伟[1] 罗小蓉[1] 张波[1] 李肇基[1] 顾晶晶[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054

出　　处：《微电子学》2008年第6期869-872,共4页Microelectronics

基　　金：国家自然科学基金重点资助项目(60436030)

摘　　要：提出了一种新型D-RESURF埋栅SOI LDMOS(EGDR-SOI LDMOS)结构,其栅电极位于P-body区的下面,可以在扩展的埋栅电极处形成多数载流子的积累层;同时,采用DoubleRESURF技术,在漂移区中引入两区的P降场层,有效降低了器件的比导通电阻,并提高了器件的击穿电压。采用二维数值仿真软件MEDICI,对器件的扩展栅电极、降场层进行了优化设计。结果表明,相对于普通SOI LDMOS,该结构的比导通电阻下降了78%,击穿电压上升了22%。A novel IYRESURF SO1 LDMOS structure with embedded gate （EGDR-SOI LDMOS） was proposed. The gate of the structure was located under P-body region, leading to majority carrier＇s accumulation on the side wall of the extended gate. A P-top layer with two zones was introduced into drift region, which reduced the specific on-resistance and increased the breakdown voltage effectively. The extended gate and P-top layer were optimized by using 2-D MEDICL Results indicated that the specific on-resistance decreased by 78% and the breakdown voltage increased by 22 %, compared to conventional SOI LDMOS.

关 键 词：功率器件 埋栅 DOUBLE RESURF S0i LDMOS 

分 类 号：TN432[电子电信—微电子学与固体电子学]