基于FPGA的高速异步FIFO存储器的设计与实现  

The design of high-speed asynchronous FIFO memory based on FPGA

作　　者：罗先哲[1] 张仁喆[2] 付大鹏[2] 

机构地区：[1]贵州大学科技学院 [2]贵州大学电子科学与信息技术学院,550025

出　　处：《中国科技信息》2009年第2期90-91,94,共3页China Science and Technology Information

摘　　要：本文在介绍异步FIFO基本原理及结构的基础上,采用Verilog HDL硬件描述语言对异步FIFO存储器进行了RTL级设计。在设计中采用格雷码对读写地址进行编码,有效的避免了亚稳态的产生;并使用ALTERA公司的集成开发环境QuartusⅡ7.0对设计进行了编译仿真,最后在该公司的Cyclone系列器件EP1C3T100C6上通过了验证。This paper presented the basic principles and structure of the asynchronous FIFO memory, and given the RTL design which based on the Verilog HDL language. In this design, it is succeed in eliminating metastability by using Gray code to coding address code. The design was compiled and simulated by ALTERA＇ s software Quartus Ⅱ 7.0. At last, it was verified by the device EPIC3T100C6 of ALTERA＇ s Cyclone family, and the result shows that ,the design is succeed.

关 键 词：异步FIFO FPGA 格雷码 亚稳态 VERILOG HDL 存储器 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TP393[自动化与计算机技术—计算机科学与技术]