提高MOS功率晶体管封装可靠性技术研究  

Improving the Reliability of Power MOSFET Package

作　　者：张国光 郑学仁[2] 张顺 张国俊 郑春扬 吴朝晖[2] 

机构地区：[1]佛山市蓝箭电子有限公司,广东佛山528000 [2]华南理工大学电子与信息学院,广东广州510640

出　　处：《电子产品可靠性与环境试验》2009年第6期1-4,共4页Electronic Product Reliability and Environmental Testing

摘　　要：功率MOS晶体管的正向导通电阻是器件的重要指标,严重影响器件的使用可靠性。从封装材料、封装工艺等方面论述功率MOS管降低导通电阻、控制空洞、提高器件可靠性的封装技术,并通过一些实例来阐述工艺控制的效果。The forward on-resistance of a VDMOS power transistor is an important parameter, which has a great effect on the device reliability. Several package techniques such as decreasing the on-resistance and controlling the voids in the solder layer to improve the reliability are discussed and illustrated with some actual examples in this paper.

关 键 词：金属-氧化物-半导体器件 功率晶体管 封装 导通电阻 器件可靠性 

分 类 号：TN386.6[电子电信—物理电子学] TN323.4