多晶硅薄膜晶体管的有效迁移率模型  

Effective Mobility Model of Polysilicon Thin-Film Transistors

作　　者：姚若河[1] 欧秀平[1] 

机构地区：[1]华南理工大学电子与信息学院,广东广州510640

出　　处：《华南理工大学学报（自然科学版）》2010年第5期61-64,共4页Journal of South China University of Technology(Natural Science Edition)

基　　金：国家自然科学基金资助项目(60776020)

摘　　要：提出一个多晶硅薄膜晶体管的有效迁移率模型.该模型同时考虑了晶体管沟道内晶粒的数目、载流子在晶粒与晶粒间界处不同的输运特性和栅致迁移率降低效应,适应于从小晶粒到大晶粒线性区的多晶硅薄膜晶体管.研究表明:当晶粒尺寸Lg<0.4μm时,其有效迁移率主要由晶粒间界控制;降低晶粒间界陷阱态密度可提高有效迁移率;减小栅氧化层厚度可增强栅压对有效迁移率的控制作用;高栅压时出现明显的有效迁移率退化效应.Proposed in this paper is an effective mobility model of polysilicon thin-film transistors,which simulta-neously takes into account the number of grains inside the transistor channel,the transport properties of carriers between grains and grain boundaries and the gate bias controlling the mobility degradation effect,and adapts to the polysilicon thin-film transistors from small grains to large ones in linear region.It is found that,when the grain size Lg is less than 0.4μm,the effective mobility is mainly controlled by the grain boundaries,that the effective mobility can be improved by reducing the trap density of grain boundaries,that decreasing the gate oxide thickness may enhance control of effective mobility by gate voltage,and that clear effective mobility degradation may occur at a high gate voltage.

关 键 词：多晶硅 薄膜晶体管 迁移率模型 晶粒间界 

分 类 号：TN321[电子电信—物理电子学]