用于智能功率集成电路的PTG-LDMOST  

A PTG-LDMOST for the Smart Power ICs Amplification

作　　者：成建兵[1] 张波[2] 李肇基[2] 

机构地区：[1]南京邮电大学微电子系,南京210046 [2]电子科技大学电子薄膜与集成器件国家重点实验室,四川成都610054

出　　处：《中国集成电路》2011年第12期51-54,59,共5页China lntegrated Circuit

摘　　要：提出一种用于智能功率集成电路的基于绝缘体上硅(SOI)的部分槽栅横向双扩散MOS晶体管(PTG-LDMOST)。PTG-LDMOST由传统的平面沟道变为垂直沟道,提高了器件击穿电压与导通电阻之间的折衷。垂直沟道将开态电流由器件的表面引向体内降低了导通电阻,而且关态的时候耗尽的JFET区参与耐压,提高单位漂移区长度击穿电压。仿真结果表明:对于相同的10微米漂移区长度,新结构的击穿电压从常规结构的111V增大到192V,增长率为73%。A new partial trench gate lateral Double-diffused MOS transistor on SOI for smart power ICs is proposed.The PTG-LDMOST changes the channel from lateral to vertical and the trade-off between the breakdown voltage and the on-resistance is improved.The on-state current transportation is changed from the device surface to the bulk of drift region because of the vertical channel.As a result,the on-resistance is decreased.Furthermore,in off-state,the breakdown voltage per drift region length is improved due to the depletion of the JFET area.Simulation results show that the breakdown voltage of the new structure is increased from 111V of the conventional structure to 192V,and the improvement rate is 73%.

关 键 词：SOI PTG-LDMOST 击穿电压 导通电阻 

分 类 号：TN386[电子电信—物理电子学]