辐照下背栅偏置对部分耗尽型绝缘层上硅器件背栅效应影响及机理分析  

Back-gate bias effect on partially depleted SOI/MOS back-gate performances under radiation condition

作　　者：周昕杰[1,2] 李蕾蕾[2] 周毅[2] 罗静[2] 于宗光[2] 

机构地区：[1]东南大学电子科学与工程学院,南京210096 [2]中国电子科技集团第五十八研究所,无锡214035

出　　处：《物理学报》2012年第20期323-329,共7页Acta Physica Sinica

基　　金：SOI研发中心基金(批准号:20106250XXX);宇航高可靠研发项目(批准号:XXX7116X);江苏省"333"科研项目(批准号:BRA2011115)资助的课题~~

摘　　要：基于部分耗尽型绝缘层上硅(SOI)器件的能带结构,从电荷堆积机理的电场因素入手,为改善辐照条件下背栅Si/SiO_2界面的电场分布,将半导体金属氧化物(MOS)器件和平板电容模型相结合,建立了背栅偏置模型.为验证模型,利用合金烧结法将背栅引出加负偏置,对NMOS和PMOS进行辐照试验,得出:NMOS背栅接负压,可消除背栅效应对器件性能的影响,改善器件的前栅I-V特性;而PMOS背栅接负压,则会使器件的前栅I-V性能恶化.因此,在利用背栅偏置技术改善SOI/NMOS器件性能的同时,也需要考虑背栅偏置对PMOS的影响,折中选取偏置电压.该研究结果为辐照条件下部分耗尽型SOI/MOS器件背栅效应的改善提供了设计加固方案,也为宇航级集成电路设计和制造提供了理论支持.According to the partially depleted SOI/MOS device＇s band gap, starting with the electric field, which is a factor of back-gate charge stack, we combine SOI device capacitance model and flat capacitance model for finding the way to keep electric field at the interface of Si/Si02, and build a back-gate bias model. For validating the new model, we use alloy-agglomeration at the back gate. After radiation experiments, we compare the results of back-gate effect on NMOS with those on PMOS. It is concluded that as far as NMOS is concerned, negative voltage at back-gate can eliminate the back-gate effect which influence the performance of device, and improves the performance of front-gate. However negative voltage at back-gate makes the performance of PMOS worse. Therefore, when we use the back-gate bias to improve the performance of device, we must consider the performances of NMOS and PMOS and compromise the choice of the voltage which is applied to the back-gate. This research supplies not only a design scheme for hardening back-gate effect of SOI devices under radiation condition, but also a support in theory for integrated circuit design and manufacture, which is used in space.

关 键 词：绝缘层上硅器件 总剂量效应 背栅效应 背栅偏置 

分 类 号：TN386[电子电信—物理电子学]