一款用于多媒体处理的异构多核系统芯片的可测试性设计  

Design-for-testability for a heterogeneous multi-core system-on-chip on multimedia processing

作　　者：刘辉聪 孟海波[1] 李华伟[1] 邓家超 李晓维[1] 

机构地区：[1]计算机体系结构国家重点实验室中国科学院计算技术研究所,北京100190 [2]中国科学院大学计算机与控制学院,北京100049

出　　处：《中国科学：信息科学》2014年第10期1239-1252,共14页Scientia Sinica(Informationis)

基　　金：国家自然科学基金(批准号:61176040;61204047);国家重点基础研究发展计划(973)(批准号:2011CB302501)资助项目

摘　　要：随着集成电路工艺的发展,系统芯片(SoC)集成已成为超大规模集成电路的主流设计方法.SoC设计具有强调自顶向下设计、突出设计重用性、重视低功耗的特点,给集成电路的可测试性设计带来了严峻的挑战.本文针对一款用于多媒体处理的异构多核系统芯片DPU-m,提出了一套完整的可测试性设计方案,支持3种工作模式:功能模式、存储器内建自测试模式以及扫描测试模式,并进行了设计实现和评估.针对逻辑电路的可测试性设计,采用自顶向下的模块化设计思想,提出并实现了一种分布式与多路选择器相结合的测试访问机制,实验结果表明,DPU-m逻辑电路单固定型故障的测试覆盖率为98.58%,满足设计方要求;针对实速时延测试的需求,设计并实现了基于片上时钟生成器的时钟控制单元,可在片上支持不同时钟域、6种时钟频率的实速时延测试;针对存储器电路的自测试,设计并实现了串并行结合的存储器内建自测试结构,在最大测试功耗的约束下有效地减少了测试时间;进一步设计了顶层测试结果输出电路,满足了设计方要求的诊断分辨率,若以100 MHz的频率进行测试,测试时间为14 ms.With the development of integrated circuit technology, system-on-chip （SoC） integration has become the mainstream method of VLSI design. SoC design usually has three features： emphasis on top-down design, outstanding design reusability, and need of low-power facilities, which brings great challenges to design for testability （DFT）. This paper proposes a complete DFT scheme for a heterogeneous multi-core system-on-chip on multimedia processing, DPU-m. The proposed DFT scheme supports three operation modes： function mode, memory built-in self-test mode （BIST） and scan test. mode. This thesis uses a top-down and modular design method for the DFT of DPU-m logic circuit. It proposes and implements a distributed and multiplexed test access meehanism; Experimental results show that test coverage of the single stuck-at fault for DPU-m logic circuit is 98.58%, which meets the requirements of the designer. In order to meet the need of at-speed testing, this thesis designs and implements an on-chip clock controller based on an on-chip clock generator, which supports at-speed testing of different clock domains. This thesis designs and implements a serial arid parallel combined BIST structure for the on-chip memory, which meets the constraints of test power and reduces test time. Then, this thesis designs and implements the test results＇ output circuit, with a memory diagnostic resolution meeting tire requirements of the designer; the results show that the test time for memories is 14 ms at the test frequency of 100 MHz.

关 键 词：可测试性设计 测试访问机制 测试调度 片上时钟控制单元 存储器内建自测试 

分 类 号：TN402[电子电信—微电子学与固体电子学]