埋层深度对Triple-RESURF LDMOS纵向电场和击穿电压的影响  被引量:1

Influences of the Buried-Layer Depth on Vertical Electric Field and Breakdown Voltage of Triple-RESURF LDMOS

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作  者:宋庆文[1] 胡夏融[1] 冯灏[1] 

机构地区:[1]西华大学物理与化学学院,成都610039

出  处:《微电子学》2015年第2期253-257,共5页Microelectronics

基  金:四川省教育厅科研项目(14ZB0132);西华大学校级重点科研项目(z1323318)

摘  要:研究了P埋层深度对体硅Triple-RESURF LDMOS纵向电场和击穿电压的影响。分析表明,当P型埋层靠近器件表面时,纵向电场平均值较小,击穿电压较低;当P型埋层靠近衬底时,优化漂移区浓度较低,器件比导通电阻较大;当P型埋层位于漂移区中部时,器件的BV2/Rs,on设计优值最大。指出了P型埋层在漂移区不同区域时击穿点的位置,以及对应的漂移区浓度取值范围,为横向高压Triple-RESURF LDMOS的设计提供了参考。The influences of the P buried-layer depth on the vertical electric field and breakdown voltage of bulksilicon triple-RESURF LDMOS was presented.The analyses results indicated that,when P layer was buried near the surface of the device,the average value of the vertical electric field was small,which resulted in a low breakdown voltage.When P layer was buried near the substrate of the device,the optimal drift doping was small,which resulted in a large specific on-resistance.The best position of the P buried-layer was in the middle of the device.The breakdown point and the corresponding range of the drift doping when P layer was buried at different position were also given.That would provide references for the design of lateral high voltage triple-RESURF LDMOS.

关 键 词:Triple-RESURF 击穿电压 LDMOS 纵向电场 

分 类 号:TN433[电子电信—微电子学与固体电子学]

 

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