单粒子翻转加固锁存器分析与辐照试验验证  

Analysis and Radiation Tests of the SEU Hardened CMOS Latches

作　　者：李天文[1,2] 杨海钢[1] 蔡刚[1] 李悦[1,2] 卢凌云[1,2] 

机构地区：[1]中国科学院电子学研究所可编程芯片与系统实验室,北京100190 [2]中国科学院大学信息科学与工程学院,北京100049

出　　处：《微电子学》2016年第2期261-266,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61271149)

摘　　要：对目前基于软错误屏蔽、施密特触发及双互锁单元结构的几种单粒子翻转加固锁存器进行分析,并从面积、延时、功耗和抗单粒子翻转能力等方面进行综合比较。着重剖析了DICE结构的多节点翻转特性,研究了敏感节点隔离对抗单粒子翻转能力的影响,设计了测试芯片,并进行了辐照试验验证。辐照试验结果表明,相比于其他加固锁存器结构,DICE结构的单粒子翻转阈值最高,翻转截面最低,功耗延时积最小。当敏感节点隔离间距由0.21μm增大到2μm时,DICE结构的单粒子翻转阈值增大157%,翻转截面减小40%,面积增大1倍。在DICE结构中使用敏感节点隔离可有效提高抗单粒子翻转能力,但在具体的设计加固中,需要在抗辐照能力、面积、延时和功耗之间进行折中考虑。Several widely used single event upset（SEU）hardened CMOS latches were analyzed,especially for the multi-node upset property of dual inter-locked cell（DICE）.Then,comparisons in area,delay and power for all these latches were carried out.To account for the multi-node upset property of DICE,three kinds of DICEs with different sensitive node distances were employed in the test chip.Radiation test results showed that DICE obtained highest SEU linear energy transfer（LET）threshold and lowest upset cross-section,compared with other hardened latches.When the separation distance of the sensitive nodes increased from 0.21μm to 2μm,DICE would obtain a 157% higher upset threshold and 40% lower SEU cross-section with an extra one times area penalty.Hence,compromise should be made between radiation harden,silicon area,delay and power consumption when the DICE was used for SEU hardening.

关 键 词：辐照效应 单粒子翻转 锁存器 辐照设计加固 双互锁结构 

分 类 号：TN432[电子电信—微电子学与固体电子学]