一种超低比导通电阻的L型栅漏极LDMOS  

An Ultralow Specific On-Resistance LDMOS with L-Shaped Gate and Drain

作　　者：石琴[1] 陈祝[1] 吴丽娟[1,2] 蔡鹏飞[1] 何航丞 

机构地区：[1]成都信息工程大学模拟电路与器件实验室,成都610225 [2]长沙理工大学,长沙410114

出　　处：《微电子学》2016年第2期277-281,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61201094)

摘　　要：提出了一种具有超低比导通电阻的L型栅漏极LDMOS器件。该器件在两个氧化槽中分别制作L型多晶硅槽栅。漏极n型重掺杂区向下延伸,与衬底表面重掺杂的n型埋层相接形成L型漏极。L型栅极不仅可以降低导通电阻,还具有纵向栅场板的特性,可有效改善表面电场分布,提高击穿电压。L型漏极为电流提供了低阻通路,降低了导通电阻。另外,氧化槽折叠漂移区使得在相同耐压下元胞尺寸及导通电阻减小。二维数值模拟软件分析表明,在漂移区长度为0.9μm时,器件耐压达到83V,比导通电阻仅为0.13mΩ·cm^2。An ultralow specific on-resistance（Ron,sp）LDMOS with L-shaped gate and drain was proposed.The device was characterized by two L-shaped poly trench gates which were inserted in the oxide trenches separately,and an n＋-buried layer（NBL）on the top of the p-substrate was contacted with the extended drain n＋ region.Lshaped trench poly gates not only reduced Ron,sp,but also acted as vertical gate field plate structure.The surface electric field distribution was effectively improved,and device breakdown voltage（VB）was further promoted.The L-shaped drain formed a low resistance path which resulted in a decreased Ron,sp.Moreover,the oxide trench folded drift region structure amplified a smaller cell pitch and Ron,sp.Two-dimensional numerical simulations had been performed to analyze the performance of the proposed device,and the parameters with VB of 83 Vand Ron,sp of 0.13mΩ·cm2 were obtained with a drift region of 0.9μm.

关 键 词：LDMOS 槽栅 比导通电阻 击穿电压 

分 类 号：TN386[电子电信—物理电子学]