薄外延CMOS芯片阱掺杂浓度与击穿电压的关系  

Research of Relationship Between Well Doping Concentration and Breakdown Voltage in Thin-Epitaxy CMOS Chips

作　　者：韩兆芳[1] 谢达[1] 乔艳敏[1] 

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子与封装》2016年第8期37-40,共4页Electronics & Packaging

摘　　要：CMOS电路由于寄生结构的影响,易于发生闩锁效应。主要通过流片实验测试验证,探讨了在外延厚度较薄的情况下阱掺杂浓度与击穿电压之间的关系。提出了在不改变外延厚度、保证芯片抗闩锁性能的前提下,提高CMOS器件击穿电压的方法。Potential parasitic structure in CMOS integrated circuits may cause latch-up effect from time to time. To solve the problem, the paper makes experiments to explore the relationship between well doping concentration and breakdown voltage in CMOS chips with thin epitaxy technique via wafer testing.Aneffective method increasing breakdown voltage of CMOS deviceswhile retaining epitaxy thickness and anti-latch-up capability is proposed.

关 键 词：CMOS集成电路 闩锁效应 外延片 穿通击穿 

分 类 号：TN432.1[电子电信—微电子学与固体电子学]