一种干法刻蚀形成高深宽比CIS Deep-P Well IMP掩模的工艺方法的探究  

Research on Dry Etch of forming High-Aspect-Ratio CIS Deep-P Well IMP Mask

作　　者：乔夫龙 耿金鹏 许鹏凯 QIAO Fulong;GENG Jinpeng;XU Pengkai(Shanghai Huali Microelectronics Co.,Ltd,Shanghai 201203,China.)

机构地区：[1]上海华力微电子有限公司,上海201203

出　　处：《集成电路应用》2018年第7期37-41,共5页Application of IC

基　　金：上海市经济和信息化委员会软件和集成电路产业发展专项基金(2015.150204)

摘　　要：为有效提升CIS(CMOS Image Sensor)器件的FWC(Full Well Capacity),需要将更高能量的DWP IMP注入到更小的space pattern区,相比较单一的光刻胶,引入TRL(TriLayer:PR/Si HM/SOC)并使用干刻方法能有效地形成了high-aspect-ratio(高深宽比,>20)的图案掩模。其中,DPW IMP阻挡掩模可以做到更厚,约4.2μm,DPW pattern的space可以做到更小,约0.2μm。该工艺革新为后续deeper DPW IMP,pixel shrinking,同时提升CIS器件的FWC光素性能提供了可能,针对引入TRL的干刻工艺的主要建立过程予以技术说明。In order to effectively improve the FWC（Full Well Capacity） of the CIS（CMOS Image Sensor） device, the higher energy DWP IMP is needed to be injected into the smaller space pattern region. The pattern mask of the ratio would be more than 20. Among them, the DPW IMP barrier mask can be thicker, about 4.2 μm, and the DPW pattern space can be smaller, about 0.2 μm. The process is innovative for subsequent deeper DPW IMP, pixel shrinking. At the same time, it is possible to enhance the FWC optical properties of CIS devices, and give technical explanation for the main establishment process of TRL dry etching process.

关 键 词：集成电路制造 干刻刻蚀 CMOS图像传感器 full WELL capacity 光素性能 HIGH-ASPECT-RATIO Deep P-WELL IMP图案掩模 高深宽比 Tri-Layer PR/SiHM/SOC 像素压缩 

分 类 号：TN405[电子电信—微电子学与固体电子学]