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作 者:张天祥 刘瑞强 周冲 刘艳莉 张艳花[1] 张鹏程[1] 桂志国[1] ZHANG Tianxiang;LIU Ruiqiang;ZHOU Chong;LIU Yanli;ZHANG Yanhua;ZHANG Pengcheng;GUI Zhiguo(Shanxi Provincial Key Laboratory for Biomedical Imaging and Big Data,North University of China,Taiyuan 030051,China;School of Electronics and Information Engineering,Harbin Institute of Technology,Harbin 150001,China;School of Information and Communication Engineering,North University of China,Taiyuan 030051,China)
机构地区:[1]中北大学生物医学成像与影像大数据山西省重点实验室,山西太原030051 [2]哈尔滨工业大学电子与信息工程学院,黑龙江哈尔滨150001 [3]中北大学信息与通信工程学院,山西太原030051
出 处:《测试技术学报》2019年第5期398-405,共8页Journal of Test and Measurement Technology
基 金:国家自然科学基金资助项目(61671413,61801438);国家重大科学仪器设备开发专项资助项目(2014YQ24044508)
摘 要:针对Perona-Malik模型图像增强算法运行在计算机CPU上无法满足算法的实时性要求的问题,基于FPGA设计了一种改进型Perona-Malik模型图像增强算法的硬件加速结构.该硬件加速结构采用行缓存实现对部分图像的缓存操作;同时通过提取出参数查找表的方式,并使用梯度的计算结果为索引,降低了硬件结构的复杂度;计算过程中采用补码和定点小数,保证了计算结果的准确性;此外采用3级流水线处理方式,增加了该硬件结构的吞吐量.实验结果表明:8次迭代处理后,在与软件处理效果相近的情况下,一帧256×256图像处理时延约为0.67 ms,满足实时处理的需求,是计算机CPU实现速度的近300倍.In view of the problem that the Perona-Malik model image enhancement algorithm can not satisfy the real-time requirement when it was implemented on the computer,a hardware acceleration structure of improved Perona-Malik model image enhancement algorithm is designed based on FPGA.First,the hardware acceleration structure uses row cache to cache some images;Meanwhile,extracting the parameter look-up table and using the result of gradient as the index reduced the complexity of the hardware architecture.During the calculation process,adopting complement numbers and fixed point decimal numbers could ensure the accuracy of the calculation results.In addition,using three-stage pipeline process increased the handling capacity of the hardware architecture.The experimental results show that the processing delay of one frame 256×256 image is 0.67 ms after 8 times iteration process.The time meets the need of real-time process and the results are similar to the software processing results.But the processing rate is 300x of the computer’s CPU.
关 键 词:图像增强 FPGA 偏微分方程 Perona-Malik模型 硬件加速
分 类 号:TP751.1[自动化与计算机技术—检测技术与自动化装置]
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