700 V超低比导通电阻的LDMOS器件  

700 V Ultra-Low Specific on-Resistance LDMOS

作　　者：李怡 乔明[1] LI Yi;QIAO Ming(State Key Laboratory of Electronic Thin Films and Integrated Device,UESTC,Chengdu 610054,China)

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054

出　　处：《电子与封装》2020年第8期43-46,共4页Electronics & Packaging

摘　　要：LDMOS器件广泛应用于高压集成电路芯片中,由于常作为功率开关来使用,其主要的性能指标为击穿电压(VB)与比导通电阻(RON,sp)。然而,VB与RON,sp均强烈受制于漂移区长度及掺杂浓度,因此存在固有的矛盾关系。Triple RESURF技术被广泛使用于优化器件VB与RON,sp之间的矛盾关系。基于传统Triple RESURF技术,提出了一种新型Triple RESURF LDMOS结构,即在P-buried层的上方和下方引入了高浓度的N型掺杂层。相较于传统结构,该结构器件既可以避免表面杂质浓度较高带来的器件提前击穿,又可以降低同等电压下的比导通电阻。测试结果表明该结构可以达到VB=795V,RON,sp=78.3 mΩ·cm2,相比于传统结构的RON,sp降低了26.8%。LDMOS devices are widely used in high voltage integrated circuit chips.Because LDMOS are often used as power switches,the main performance indicators are breakdown voltage(VB)and specific on-resistance(RON,sp).However,VB and RON,sp are strongly subject to the length of drift zone and doping concentration,so there is an inherent contradictory relationship between VB and RON,sp.Triple RESURF technology is widely used to optimize the contradictory relationship between VB and RON,sp.Based on the traditional Triple RESURF technology,a new Triple RESURF LDMOS structure is proposed,which introduces high concentration N-type layer above and below the P-buried layer.Compared with the traditional structure,this structure can not only avoid the premature avalanche breakdown of the device caused by high surface impurity concentration,but also reduce the specific on-resistance under the same voltage.Test results show that the structure can achieve VB=795 V,RON,sp=78.3 mΩ·cm2,and compared with the traditional structure,RON,sp was reduced by 26.8%.

关 键 词：LDMOS Triple RESURF 比导通电阻 击穿电压 

分 类 号：TN306[电子电信—物理电子学]