芯粒测试技术综述  

Overview of Chiplet Testing Technology

作　　者：解维坤 蔡志匡[3] 刘小婷[3] 陈龙 张凯虹 王厚军 XIE Weikun;CAI Zhikuang;LIU Xiaoting;CHEN Long;ZHANG Kaihong;WANG Houjun(School of Automation Engineering,University of Electronic Science and Technology of China,Chengdu 610097,China;China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China;School of Integrated Circuit Science and Engineering,Nanjing University of Posts and Telecommunications,Nanjing 210003,China;Wuxi Zhongwei Tengxin Electronics Co.,Ltd.,Wuxi 214000,China)

机构地区：[1]电子科技大学自动化学院,成都610097 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035 [3]南京邮电大学集成电路科学与工程学院,南京210003 [4]无锡中微腾芯电子有限公司,江苏无锡214000

出　　处：《电子与封装》2023年第11期1-11,共11页Electronics & Packaging

基　　金：国家自然科学基金(U23B2042)。

摘　　要：随着半导体工艺的发展,芯片工艺提升愈发困难,摩尔定律日趋放缓,而芯粒集成技术促进了多芯片封装的发展,有效地延续了摩尔定律。以2.5D、3D集成为主的芯粒异构集成芯片的测试方法与传统2D芯片测试有所不同,带来一些新的测试挑战。从当前芯粒测试的挑战分析入手,介绍了芯粒互联标准、互联测试和基于不同测试访问标准的可测性设计(DFT)方法,着重阐述各方法的优缺点以及相互之间的联系与区别,旨在帮助读者对芯粒测试技术进行系统性了解。With the development of semiconductor process,chip process upgrading is more and more difficult,and Moore's law is slowing down.Chiplet integration technology has promoted the development of multichip packaging,effectively continuing Moore's law.The testing methods of Chiplet heterogeneous integrated chips,which are mainly based on 2.5D and 3D integration,are different from traditional 2D chip testing,bringing some new testing challenges.Starting with the analysis of the challenges of current Chiplet testing,Chiplet interconnection standards,interconnection testing and design for testability(DFT)methods based on different testing access standards are introduced,focusing on the advantages and disadvantages of each method as well as the connections and differences among them,aiming to help readers gain a systematic understanding of Chiplet testing technology.

关 键 词：芯粒 可测性设计 TSV 互联测试 先进封装 

分 类 号：TN407[电子电信—微电子学与固体电子学]