24 Gbit/s 0.2μm PHEMT复接器  

24 Gbit/s multiplexer using 0.2 μm PHEMT technology

作　　者：杨守军[1] 王志功[1] 朱恩[1] 冯军[1] 熊明珍[1] 夏春晓[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《东南大学学报（自然科学版）》2004年第3期289-292,共4页Journal of Southeast University：Natural Science Edition

基　　金：国家高技术研究发展计划 (863计划 )资助项目(2 0 0 1AA3 12 0 60 )

摘　　要：本文利用Philips公司OMMIC 0 2 μmGaAsPHEMT工艺 ,设计出 2 4Gbit/s的复接器 .应用源极耦合FET逻辑 (SCFL) ,使逻辑电路能够在 2 4Gbit/s速率上正常工作 .时钟采用二倍频方案 ,解决了多级复接中的高速时钟问题 .改进异或门拓扑结构实现的二倍频器 ,结构简单、实用 ,降低了电路复杂度 .利用源极耦合电容的微分作用 ,加速晶体管开、关转换 ,提高了选择器工作速度 .芯片通过功能测试验证 ,数据速率可达到 2 4Gbit/s.A 24 Gbit/s multiplexer is realized by using OMMIC 0.2 μm pseudomorphic high electron mobility transistor (PHEMT) GaAs technology of Philips. This circuit is designed with source-coupled field effect transistor logic (SCFL) structure. The clock signal is obtained by using a frequency doubler which uses a modified XOR topology, so that the complexity of the system is reduced. The speed of the selector is accelerated by applying a source-coupled capacitor which speeds up the PHEMT switches. The test results of the function verify that this chip can correctly work at 24 Gbit/s.

关 键 词：光通信 复接器 SCFL 倍频器 

分 类 号：TN492[电子电信—微电子学与固体电子学]