ALL-DIGITAL

作品数：14被引量：10H指数：2
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相关期刊：《High Technology Letters》《Chinese Optics Letters》《Semiconductor Photonics and Technology》《Journal of Semiconductors》更多>>
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A 16-bit 1 MSPS SAR ADC with foreground calibration and residual voltage shift strategy被引量：1
《Journal of Semiconductors》2020年第12期41-49,共9页Xian Zhang Xiaodong Cao Xuelian Zhang 
In this paper,a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter(SAR ADC)is developed by the CMOS 0.25μm process.An on-chip all-digital foreground weights calibration ...
关键词：foreground all-digital calibration RS strategy RS-based dither auto-zero comparator SAR ADC 
A high-accuracy DCO with hybrid architecture
《Journal of Semiconductors》2017年第7期111-116,共6页Yapeng Sun Huidong Zhao Shushan Qiao Yong Hei Fuhai Zhang 
supported by the National Natural Science Foundation of China(Nos.61306025,61474135)
In this paper, a novel hybrid digital-controlled oscillator（DCO） is proposed, which is used to improve the accuracy of the all-digital clock generator without reference source. The DCO with hybrid architecture consi...
关键词：high accuracy DCO all-digital PVT variations 
An all-digital synthesizable baseband for a delay-based LINC transmitter with reconfigurable resolution
《Journal of Semiconductors》2014年第11期98-106,共9页韩越 乔树山 黑勇 
The linear amplification with nonlinear component transmitter is a promising solution to high efficiency and high linearity amplification for non-constant envelope signals. An all-digital synthesizable baseband for a ...
关键词：low power linear amplification with nonlinear component （LINC） ALL-DIGITAL synthesizable 
A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology
《Journal of Semiconductors》2013年第3期81-85,共5页江晨 黄煜梅 洪志良 
supported by the Important National Science and Technology Specific Projects of China(No.2009ZX01031-003-002)
A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input sta...
关键词：time-to-digital converter gated ring oscillator effective resolution all-digital phase locked loop 
A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA
《Journal of Semiconductors》2011年第10期139-146,共8页陈柱佳 杨海钢 刘飞 王瑜 
Project supported by the Major National Scientific Research Plan of China(No.2011 CB933202);the National High Technology Research and Development Program of China(No.2008AA010701)
A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS） c...
关键词：all digital DLL DDR SDRAM controller time-to-digital converter duty cycle corrector DCDL FPGA 
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