云南高校图书馆联盟文献共享服务平台- FLOORPLAN

FLOORPLAN: 作品数：11被引量：6H指数：1; 导出分析报告; 相关作者：董社勤杨柳黄金明洪先龙苏琦更多>>; 相关机构：清华大学国家高性能集成电路（上海）设计中心国防科学技术大学中国科学院大学更多>>; 相关期刊：《Journal of Computer Science & Technology》《Circuits and Systems》《中国集成电路》《微电子学与计算机》更多>>; 相关基金：国家自然科学基金香港特区政府研究资助局资助项目霍英东教育基金更多>>

A Machine Learning Framework with Feature Selection for Floorplan Acceleration in IC Physical Design被引量：1: 《Journal of Computer Science & Technology》2020年第2期468-474,共7页Shu-Zheng Zhang Zhen-Yu Zhao Chao-Chao Feng Lei Wang; This work was supported by the HeGaoJi Program of China under Grant Nos.2018ZX01029103 and 2017ZX01038104-002;the National Natural Science Foundation of China under Grant Nos.61802427 and 61902408.; Floorplan is an important process whose quality determines the timing closure in integrated circuit(IC)physical design.And generating a floorplan with satisfying timing result is time-consuming because much time is sp...; 关键词：physical DESIGN machine learning FEATURE selection DESIGN space EXPLORATION

Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm: 《Circuits and Systems》2016年第5期562-573,共12页Sivaranjani Paramasivam Senthilkumar Athappan Eswari Devi Natrajan Maheswaran Shanmugam; Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimat...; 关键词：VLSI Non-Slicing Floorplan Modified Corner List (MCL) Algorithm Hybrid Particle Swarm Optimization-Harmony Search Algorithm (HPSOHS)

基于高层LISA功耗模型的RISC处理器热量分析与仿真方法: 《微电子学与计算机》2015年第8期125-129,134,共6页岳丹徐抒岩聂海涛王刚; 中科院长春光机所创新基金(Y2CX1SS125); 为了优化集成电路芯片的布局封装,提高芯片性能及可靠性,对处理器级别的实时片上温度调节技术进行评估,给出了一种实时计算芯片单元模块功耗和温度的仿真方法.采用高层LISA功耗模型,得到RISC处理器上通用应用程序的实时功耗;利用芯片后...; 关键词：HOTSPOT 热量分析 LISA功耗模型芯片floorplan

快速buffer添加算法被引量：1: 《中国集成电路》2008年第10期32-36,共5页苏琦黄金明; 在深亚微米设计中,连线延迟时间已经超过器件延迟时间,成为影响性能的瓶颈之一。在线网中插入缓冲器(buffer)是改善线延迟的一种有效方法,但是目前基于缓冲器块(buffer block)的方法一般因其计算量比较大,算法比较慢,并且也增加布局(flo...; 关键词：互连线 FLOORPLAN buffer添加

基于Astro的MIC总线控制器专用集成电路后端设计: 《集成电路通讯》2007年第3期16-20,共5页陈洁王丽丽; 本文介绍了采用当前ASIC设计领域内流行的后端布局布线工具—Astro,进行MIC总线控制器远程模块专用集成电路的设计过程。; 关键词：Astro自动布局布线工具时钟树综合(CTS) 布局(Floorplan) 布线(Placement)

Thermal-Aware Floorplanning Considering Empty Space Effect Based on Genetic Algorithms: 《Chinese Journal of Electronics》2007年第3期429-434,共6页LIU Yongpan YANG Huazhong LUO Rong WANG Hui; This work is supported by the National Natural Science Foundation of China （No.90207001, No.60506010） and National 863 Project of China （No.2004AA1Z1050, No.2005AA1Z1230）.; As power density increases steadily, temperature has become an important design concern. One of the most effective ways to reduce chip peak temperature is thermal-aware fioorplanning, in which thermal analysis has to ...; 关键词：Thermal-aware floorplan Empty space effect Compact resistive thermal model Genetic algorithms

Physical design method of MPSoC: 《Journal of Zhejiang University-Science A(Applied Physics & Engineering)》2007年第4期631-637,共7页LIU Peng XIA Bing-jie TENG Zhao-wei; Project supported by the Hi-Tech Research and Development Pro-gram (863) of China (No. 2002AA1Z1140);the Fok Ying TongEducation Foundation (No. 94031), China; Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Cus...; 关键词：Physical design Fast prototyping FLOORPLAN Clock tree synthesis （CTS） Power plan Multiprocessor system-onchip （MPSoC）

FIDER: A Force-Balance-Based Interconnect Delay Driven Re-Synthesis Algorithm for Data-Path Optimization After Floorplan: 《Tsinghua Science and Technology》2007年第1期63-69,共7页王云峰边计年洪先龙周强吴强; the National Natural Science Foundation of China (Nos. 90407005, 90207017, 60236020, and 60121120706); As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-syn...; 关键词：high-level synthesis FLOORPLAN interconnect delay re-synthesis reschedule REALLOCATION

An Incremental Algorithm for Non-Slicing Floorplan Based on Corner Block List Representation被引量：1: 《Journal of Semiconductors》2005年第12期2335-2343,共9页杨柳马昱春洪先龙董社勤周强; 国家自然科学基金(批准号:90407005,60473126);Intel公司3D布图规划和布局资助项目~~; We present a novel incremental algorithm for non-slicing floorplans based on the corner block list representation. The horizontal and vertical adjacency graphs are derived from the packing of the initial floorplanning...; 关键词：incremental floorplanning corner block list adjacency graph balance node

Fast Evaluation of Bounded Slice-Line Grid: 《Journal of Computer Science & Technology》2004年第6期973-980,共8页SongChen Xian-LongHong She-QinDong Yu-ChunMa Chung-KuanCheng JunGu; 国家自然科学基金，香港研究资助局资助项目，美国国家自然科学基金，国家高技术研究发展计划(863计划); Bounded Slice-line Grid (BSG) is an elegant representation of block placement, because it is very intuitionistic and has the advantage of handling various placement constraints. However, BSG has attracted little atten...; 关键词：BSG FLOORPLAN PLACEMENT VLSI

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