financial support under the R&D project scheme. No: 1950/CST/R&D/Phy & Engg Sc/2015 27th Aug 2015
Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory arch...
This paper presents a 4×2 switching matrix implemented in the Win 0.5 μm Ga As pseudomorphic high electron mobility transistor process, it covers the 0.5–3 GHz frequency range. The switch matrix is composed of 4 SP...
We demonstrate a directed optical decoder device consisting of two cascaded microring resonators, which are both modulated through the plasma dispersion effect. The inherent resonance wavelength mismatch between two m...
Project supported by the National High Technology Research and Development Program of China(No2006AA01Z239)
A fully pipelined 10 B/8 B decoder is presented with shorter critical path than before,and so its speed is improved greatly.Based on the proposed architecture,a 10 B/8 B decoder is implemented based on standard cells ...
A fully integrated CMOS bio-chip is designed in a SMIC 0.18μm CMOS mixed signal process and successfully integrated with a novel bio-nano-system. The proposed circuit integrates an array of 4 × 4 (16 pixels) of 19...
The first domestic total dose hardened 2μm partially depleted silicon-on-insulator (PDSOI) CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transisto...