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DESIGN_AND_ANALYSIS: 作品数：259被引量：446H指数：10; 导出分析报告; 相关作者：王松涛羌晓青王仲奇冯国泰陈淑燕更多>>; 相关机构：东南大学哈尔滨工业大学东北师范大学东华大学更多>>; 相关期刊：更多>>; 相关基金：国家自然科学基金国家高技术研究发展计划中国博士后科学基金国家重点基础研究发展计划更多>>

A routing algorithm for FPGAs with time-multiplexed interconnects: 《Journal of Semiconductors》2020年第2期73-82,共10页Ruiqi Luo Xiaolei Chen Yajun Ha; Previous studies show that interconnects occupy a large portion of the timing budget and area in FPGAs.In this work,we propose a time-multiplexing technique on FPGA interconnects.In order to fully exploit this interco...; 关键词：field programmable gate arrays digital integrated circuits routing algorithm design and analysis

The design and analysis of a MEMS electrothermal actuator: 《Journal of Semiconductors》2015年第4期90-94,共5页王锁成郝永平刘双杰; This paper introduces a type of out-of-plane microelectrothermal actuator, which is based on the principle of bimetal film thermal expansion in the fuse. A polymer SU-8 material and nickel are used as the functional a...; 关键词：bimetal film electrothermal actuator thermal expansion SU-8 Coventorware stress check

Design and analysis of 20 Gb/s inductorless limiting amplifier in 65 nm CMOS technology被引量：1: 《Journal of Semiconductors》2014年第10期91-97,共7页何睿许建飞闫娜孙杰边历嵌闵昊; Project supported by the National High Technology Research and Development Program of China(No.2011AA010404);the GeneralProgram for International Science and Technology Cooperation Projects of China(No.2010DFB13040);the National Natural Science Foundation of China(No.61076028);the Doctoral Program of Higher Education of China(No.20100071120026); A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier...; 关键词：inductorless limiting amplifier optical communication interleaving feedback DCOC

Design and analysis of a dual mode CMOS field programmable analog array: 《Journal of Semiconductors》2014年第10期152-162,共11页程小燕杨海钢尹韬吴其松张洪锋刘飞; Project supported by the CAS/SAFEA International Partnership Program for Creative Research Teams and the National High Technology Research and Development Program of China(No.2012AA012301); This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connectio...; 关键词：field-programmable gate array field-programmable analog array configurable analog block rail-to- rail biquadratic filters

Design and analysis of a three-stage voltage-controlled ring oscillator: 《Journal of Semiconductors》2013年第11期112-117,共6页雷雪梅王志功沈连丰; supported by the Research Project of Science and Technology at Universities of Inner Mongolia Autonomous Region(No.NJZY11016);the Innovation Fund of Ministry of Science&Technology for Small and Medium Sized Enterprises,China(No.11C26213211234); This paper describes a large tuning range low phase noise voltage-controlled ring oscillator （ring VCO） based on a different cascade voltage logic delay cell with current-source load to change the current of output ...; 关键词：large tuning rang ring VCO different cascade voltage logic low phase noise

Design and analysis of a bang-bang PLL for 6.25 Gbps SerDes: 《Journal of Semiconductors》2012年第12期73-80,共8页周明珠; Project supported by the Zhejiang Provincial Natural Science Foundation of China(No.Y1110991);the National Natural Science Foundation of China(No.61102027);the Start Research Foundation of Hangzhou Dianzi University(No.KYS045609050); An analysis illustrates the loop nonlinear performance in a bang-bang PLL. A third-order equivalent model is deduced to give an approximate evaluation of the loop parameters. The architecture of the proposed phase det...; 关键词：PLL bang-bang PD LC VCO

Design and analysis of a highly-integrated CMOS power amplifier for RFID readers: 《Journal of Semiconductors》2009年第6期121-125,共5页高同强张春池保勇王志华; To implement a fully-integrated on-chip CMOS power amplifier（PA） for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as...; 关键词：CMOS power amplifier RFID reader matching network bonding wires

Design and analysis of a UWB low-noise amplifier in the 0.18μm CMOS process: 《Journal of Semiconductors》2009年第1期39-43,共5页杨袆高茁杨丽琼黄令仪胡伟武; supported by the National Natural Science Foundation of China (Nos. 60673146, 60703017, 60736012, 60801045);the NationalHigh Technology Research and Development Program of China (No. 2007AA01Z114);the State Key Development Program for BasicResearch of China (No. 2005CB321600); An ultra-wideband （3.1-10.6 GHz） low-noise amplifier using the 0.18μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consu...; 关键词：ULTRA-WIDEBAND low-noise amplifier CMOS

Design and Analysis of a Gain-Enhanced,Fully Differential Telescopic Operational Transconductance Amplifier被引量：3: 《Journal of Semiconductors》2008年第2期269-274,共6页姚志健马成炎叶甜春莫太山; This paper describes the design and analysis of a fully differential,gain-enhanced CMOS telescopic operational transconductance amplifier （OTA） used in a pipeline analog-to-digital converter （ADC）. Specifications ...; 关键词：OTA GAIN-BOOST CMFB

Design and Analysis of Analog Front-End of Passive RFID Transponders被引量：5: 《Journal of Semiconductors》2006年第6期999-1005,共7页胡建赟何艳闵昊; 家高技术研究发展计划资助项目(批准号:2003AA1Z1280)~~; An analog front-end of HF passive RFID transponders compatible with ISO/IEC 18000-3 is presented.Design considerations, especially the power transmission in the RFID transponder, are analyzed. Based on these considera...; 关键词：RFID analog front-end power transmission ARCHITECTURE low power

DESIGN_AND_ANALYSIS