100V体硅N-LDMOS器件研究  

Research on the 100 V Bulk-Silicon N-LDMOS

作　　者：许坚[1] 孙伟峰[1] 李海松[1] 

机构地区：[1]东南大学集成电路学院,南京210096

出　　处：《电子器件》2008年第2期469-471,475,共4页Chinese Journal of Electron Devices

摘　　要：为了设计一款100V体硅N-LDMOS器件,通过借助Tsuprem-4和Medici软件详细讨论分析了高压N-LDMOS器件衬底浓度、漂移区参数、金属场极板长度等与击穿电压、开态电阻之间的关系,最终得到兼容体硅标准低压CMOS工艺的100V体硅N-LDMOS最佳结构、工艺参数。折衷考虑到了击穿电压、开态电阻这一对矛盾体以满足设计指标。通过模拟曲线可知该高压器件的关态和开态的击穿电压都达到要求,开启电压为1.5V,而且完全兼容国内体硅标准低压CMOS工艺,可以很好地应用于各种高压功率集成芯片。The relations of the breakdown voltage and Ron to the substrate concentration for the 100 V BulkSilicon N-LDMOS device,the drift parameter and themetal-filed-plate length discussed with the two softwares：. Tsuprem-4 and Medici. For the purpose of design＇s target, the final design is a compromise between the breakdown voltage and Ron. The optimal 100 V bulk-silicon N-LDMOS,which was compatible with the standard low voltage CMOS process,was proposed after the simulationson of the parameters of the N-LDMOS. The breakdown voltages of the given N-LDMOS exceed intention both in the off-state and on-state, which can be seen from the simulated curves. The threshold voltage of the N-LDMOS is 1.5 V. The presented N-LDMOS can be well applied in the high voltage power ICs for its simple process that is compatible with the CMOS process.

关 键 词：功率器件 漂移区 金属场极板 击穿电压 体硅 

分 类 号：TN386[电子电信—物理电子学]