SiC MESFET工艺技术研究与器件研制  

Study on the Process and Manufaction of SiC MESFET

作　　者：商庆杰[1] 潘宏菽[1] 陈昊[1] 霍玉柱[1] 杨霏[1] 默江辉[1] 冯震[1] 

机构地区：[1]中国电子科技集团公司第十三研究所专用集成电路国家重点实验室,石家庄050051

出　　处：《半导体技术》2009年第6期549-552,共4页Semiconductor Technology

基　　金：国家重点实验室基金项目(9140C0607010704)

摘　　要：针对SiC衬底缺陷密度相对较高的问题,研究了消除或减弱其影响的工艺技术并进行了器件研制。通过优化刻蚀条件获得了粗糙度为2.07nm的刻蚀表面;牺牲氧化技术去除刻蚀带来的表面损伤层,湿氧加干氧的氧化方式生长的SiO2钝化膜既有足够的厚度又保证了致密性良好的界面,减小了表面态对栅特性和沟道区的影响,获得了理想因子为1.17,势垒高度为0.72eV的良好的肖特基特性;等平面工艺有效屏蔽了衬底缺陷对电极互连引线的影响,减小了反向截止漏电流,使器件在1mA下击穿电压达到了65V,40V下反向漏电流为20μA。为了提高器件成品率,避免或减小衬底缺陷深能级对沟道电流的影响,使用该工艺制备的小栅宽SiC MESFET具有195mA/mm的饱和电流密度,-15V的夹断电压。初步测试该器件有一定的微波特性,2GHz下测试其最大输出功率为30dBm,增益大于5dB。To avoid the influence of high defect density on SiC substrate, the manufacturing process was studied for reducing the defects. RMS of the etching surface was about 2.07 nm by optimizing the etching. The affected layers bringing by etching was removed through sacrificial oxidation. The influence of surface state to gate characteristic and channel region was reduced by wetting oxidation adding dry oxidation. This oxidation can obtain enough thickness of SiO2 and ensure the good compact interface, so the better Schottky characteristic was obtained. The ideal factor of Schottky was 1.17 as well as the barrier height was 0.72 eV. Through the isoplanar technology, the influence of defect to leading wire of electrode became lessened and the reverse leak current was decreased, the 65 V/1 mA of breakdown voltage of device was obtained. Two different gate width devices with excellent direct current characteristic were fabricated successfully.

关 键 词：碳化硅 金属-半导体场效应晶体管 牺牲氧化 干法刻蚀 等平面工艺 

分 类 号：TN386[电子电信—物理电子学]