非晶硅薄膜晶体管基于表面势的栅电容模型  

A Surface Potential Based Gate Capacitance Model for Amorphous Si Thin Film Transistors

作　　者：刘远[1,2] 姚若河[2] 李斌[2] 

机构地区：[1]广东工业大学材料与能源学院,广州510006 [2]华南理工大学电子与信息学院,广州510640

出　　处：《微电子学》2011年第2期304-309,共6页Microelectronics

基　　金：国家自然科学基金资助项目(60776020);广东工业大学博士启动项目(4051105006)

摘　　要：基于Lambert W函数,推导出非晶硅薄膜晶体管表面势的解析解,并将其与泊松方程的数值解进行对比。结果显示:该求解大大提高了计算效率,且精确度极高。基于有效温度近似,并利用所求解到的表面势,建立器件的栅电容模型。该模型可连续、准确地描述a-Si∶H TFT在所有工作区的动态特性。最后,将模型结果与实验数据进行了对比,两者拟合良好。An analytical model of gate capacitance for a-Si∶H TFT based on surface potential was presented.Using Lambert W function,physical based analytical solution to surface potential of a-Si∶H TFT as a function of terminal voltages was derived without any empirical smooth functions.Its high accuracy in predicting surface potential under various biases was verified by comparison with numerical results from Poison equations.A gate capacitance model was developed based on the analytical solution and effective temperature approch.The improved model,which could describe all operation regions with a unique formula,was verified by a reasonable agreement between simulated results and experimental data.

关 键 词：非晶硅薄膜晶体管 栅电容 表面势 

分 类 号：TN321[电子电信—物理电子学]