GaN功率MMIC背面通孔工艺优化及可靠性分析  

Via-hole Etch Process Optimization and Reliability Analysis for GaN Power MMIC

作　　者：刘海琪[1] 王泉慧[1] 焦刚[1] 任春江[1] 陈堂胜[1] 

机构地区：[1]南京电子器件研究所,南京210016

出　　处：《固体电子学研究与进展》2011年第5期438-441,488,共5页Research & Progress of SSE

摘　　要：介绍了改进GaN功率MMIC背面通孔工艺的相关方法,并对通孔进行了可靠性方面的测试与分析。通过优化机械研磨的方法,减薄圆片至75μm左右,保持片内不均匀性在4%以内;利用ICP对基于SiC衬底的GaN功率MMIC进行了背面通孔工艺的优化,减少了孔底的柱状生成物。随后的可靠性测试测得圆片通孔的平均电阻值为6.3 mΩ,平均电感值为17.2 nH;对通孔样品在0.4 A工作电流175°C节温下进行了工作寿命试验,200 h后通孔特性无明显退化。The method of improving via-hole process was for GaN power MMIC presented.Experiments were carried out to evaluate the reliability of the process.The wafer was thinned to 75 μm with nonuniformity under 4% within a wafer.The via-hole process was optimized by inductively coupled plasma（ICP） technology to decrease pillars.The reliability test showed an average resistance of 6.3 mΩ and an average inductance of 17.2 nH;Life test carried out on the via-hole sample with 0.4 A operating current and 175°C junction temperature showed no obvious change in via-hole character after 200 hours operation.

关 键 词：背面通孔 氮化镓/碳化硅 ICP刻蚀 可靠性 

分 类 号：TN304[电子电信—物理电子学] TN306