薄膜SOI上大于600 V LDMOS器件的研制  

Study of LDMOS Device over 600 V on Thin Film SOI

作　　者：王中健[1,2] 夏超[1,2] 徐大伟[1,2] 程新红[1] 宋朝瑞[1] 俞跃辉[1] 

机构地区：[1]中国科学院上海微系统与信息技术研究所信息功能材料国家重点实验室,上海200050 [2]中国科学院研究生院,北京100049

出　　处：《半导体技术》2012年第4期254-257,共4页Semiconductor Technology

基　　金：国家自然科学基金资助项目(10775166;61006088);国家部委基金项目

摘　　要：针对600 V以上SOI高压器件的研制需要,分析了SOI高压器件在纵向和横向上的耐压原理。通过比较提出薄膜SOI上实现高击穿电压方案,并通过仿真预言其可行性。在埋氧层为3μm,顶层硅为1.5μm的注氧键合(Simbond)SOI衬底上开发了与CMOS工艺兼容的制备流程。为实现均一的横向电场,设计了具有线性渐变掺杂60μm漂移区的LDMOS结构。为提高纵向耐压,利用场氧技术对硅膜进行了进一步减薄。流片实验的测试结果表明,器件关态击穿电压可达600 V以上(实测832 V),开态特性正常,阈值电压提取为1.9 V,计算开态电阻为50Ω.mm2。In order to fabricate over 600 V high voltage devices on the SOI wafer, the withstand voltage theory of the SOI device was analyzed from horizontal and vertical aspects. Realization of high voltage on thin film SOI was proposed and verified processes were designed and implemented successfully with 1.5 um top silicon and 3 um buried oxide layer by simulation. CMOS compatible SOI LDMOS on Simbond （SIMOX and bonding） SOI wafers An optimized 60 um drift region implant mask was designed to realize a linearly graded doping profile, and silicon thickness in the drift region was reduced further by the thick field oxide process. The results show that the off-state breakdown voltage of SOI LDMOS is 832 V, the threshold voltage is 1.9 V, and the specific on-resistance is 50 Ω· mm2.

关 键 词：绝缘体上硅 横向扩散金属氧化物半导体 击穿电压 线性渐变掺杂 注氧键合 

分 类 号：TN929.533[电子电信—通信与信息系统]