SiGe MOS器件SiO_2栅介质低温制备技术研究  

Low Temperature Preparation of SiO_2 Gate Insulators for SiGe PMOS Devices

作　　者：李竞春[1] 杨沛峰[1] 杨谟华[1] 谭开洲[2] 何林[2] 郑娥[2] 

机构地区：[1]电子科技大学,四川成都610054 [2]信息产业部电子第二十四研究所,重庆400060

出　　处：《微电子学》2001年第3期192-194,共3页Microelectronics

基　　金：模拟集成电路国家重点实验室资助项目

摘　　要：为了获得电学性能良好的 Si Ge PMOS Si O2 栅介质薄膜 ,采用等离子体增强化学汽相淀积 (PECVD)工艺 ,对低温 30 0°C下薄膜制备技术进行了研究。实验表明 ,采用适当高温、短时间对PECVD薄膜退火有助于降低薄膜中正电荷密度和界面态密度。该技术用于 Si Ge PMOS研制 ,在30 0 K常温和 77K低温下 ,其跨导分别达到 45m S/mm和 92 .5m S/mm(W/L=2 0 μm/2 μm)WT5”BZ]Low temperature (300 °C) preparation of thin films is investigated to obtain thin SiO 2 gate insulators for SiGe PMOSFET's with good electrical properties Plasma Enhanced Chemical Vapor Deposition (PECVD) has been employed to prepare thin gate insulators It is shown that the interface state density and the positive charge density decline after annealing at high temperature for a short time SiGe PMOS devices fabricated by using this technology have a trans conductance of 45 mS/mm and 92 5 mS/mm at 300 K and 77 K, respectively [WT5HZ]

关 键 词：栅介质薄膜 低温制备 锗化硅 MOS器件 二氧化硅 

分 类 号：TN304.055[电子电信—物理电子学] TN386