工艺阱深对CMOS集成电路抗闩锁性能的影响  

Effect of Process Well Depth on Latch-up Characteristics in CMOS IC

作　　者：韩兆芳[1] 虞勇坚[1] 

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子与封装》2014年第6期45-47,共3页Electronics & Packaging

摘　　要：闩锁效应是体硅CMOS电路中最为严重的失效机理之一,而且随着器件特征尺寸越来越小,使得CMOS电路结构中的闩锁效应日益突出。以P阱CMOS反相器和CMOS集成电路的工艺结构为基础,采用可控硅等效电路模型,较为详细地分析了闩锁效应的形成机理,并利用试验证实,通过加深P阱深度,可以明显提升CMOS电路的抗闩锁性能。Latch-up effect is one of the most important failure mechanisms in CMOS IC with silicon substrate. And Latch-up in CMOS IC is stand out increasingly with device channel length becoming smaller and smaller. Based on CMOS inverter in P-well and the structure of CMOS IC process, SCR equivalent circuit model is adopted to analyze the mechanism of latch-up in detail. It is proved by experiments that latch up immunity of CMOS IC can be improved obviously by increase of P-well depth.

关 键 词：P阱 闩锁效应 可控硅 CMOS集成电路 

分 类 号：TN433[电子电信—微电子学与固体电子学]