基于CPU和DDR芯片的SiP封装可靠性研究  

Reliability study of system in package consisting of CPU and DDR chips

作　　者：唐宇[1,2] 廖小雨[2] 骆少明[1] 王克强[1] 李国元[2] 

机构地区：[1]仲恺农业工程学院自动化学院,广东广州510225 [2]华南理工大学电子与信息学院,广东广州510640

出　　处：《电子元件与材料》2015年第4期79-83,共5页Electronic Components And Materials

基　　金：中国博士后科学基金项目资助(No.2014M552193);中央高校基本科研业务费项目资助(自然科学类)博士启动项目资助(No.2014ZB0032);广东省自然科学基金项目资助(No.S2013020012890);广东省科技计划项目资助(No.2013B010403003)

摘　　要：利用Abaqus有限元分析方法分析了温度循环条件下CPU和DDR双芯片SiP封装体的应力和应变分布。比较了相同的热载荷下模块尺寸以及粘结层和塑封体的材料属性对SiP封装体应力应变的影响。结果表明,底层芯片、粘结层和塑封体相接触的四个边角承受最大的应力应变。芯片越薄,SiP封装体所承受的应力越大;粘结层越薄,SiP封装体所承受的应力越小。塑封体的材料属性比粘结层的材料属性更显著影响SiP封装体应力应变,当塑封体的热膨胀系数或杨氏模量越大时,SiP封装体所受应力也越大。Finite element analysis（FEA） software Abaqus was used to analyze the stress and strain distribution of system in package（SiP） consisting of CPU and DDR chips under the condition of temperature cycle. Under the same thermal load condition, the effects of the thickness of die, and the material properties of the adhesive layer and the epoxy molding compound（EMC） on stress and strain of SiP model were investigated in this study. Results show that the maximum stress and strain of SiP model are concentrated on the corner of the bottom die and the interface of the adhesive layer and EMC. With a decrease of the thickness of die, the thermal stress of SiP model increases. In contrast, with a decrease of the thickness of the adhesive layer, the stress decreases. Results also reveal that the material properties of the EMC strongly affect the stress and strain of SiP model comparing to the material properties of the adhesive layer. With an increase in the thermal expansion coefficient or Yong’s modulus of the EMC, the thermal stress of SiP model increases.

关 键 词：系统级封装 可靠性 温度循环 应力 应变 有限元分析 

分 类 号：TN305[电子电信—物理电子学]