在晶元级Si衬底上制备高深宽比SiO_2周期图形（英文）  

Fabrication of Periodic SiO_2 Pattern with High Aspect Ratio on Wafer-Scaled Si Substrate

作　　者：戚永乐[1,2,3] 张瑞英[1,2] 仇伯仓 王逸群[5] 王庶民[6] Qi Yongle Zhang Ruiying Qiu Bocang Wang Yiqun Wang Shumin(Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Suzhou 215123, China Nano-Device and Materials Division, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Suzhou 215123, China Nano Science and Technology Institute, University of Science and Technology of China, Suzhou 215123, China Research Institute of Tsinghua University in Shenzhen, Shenzhen 518055, China Nano Fabrication Facility, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Suzhou 215123, China State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China)

机构地区：[1]中国科学院苏州纳米技术与纳米仿生研究所纳米器件与应用重点实验室,苏州215123 [2]中国科学院苏州纳米技术与纳米仿生研究所纳米器件及相关材料研究部,苏州215123 [3]中国科学技术大学纳米学院,苏州215123 [4]清华大学深圳研究院,深圳518055 [5]中国科学院苏州纳米技术与纳米仿生研究所纳米加工平台,苏州215123 [6]中国科学院上海微系统所信息功能材料国家重点实验室,上海200050

出　　处：《纳米技术与精密工程》2016年第6期395-401,共7页Nanotechnology and Precision Engineering

基　　金：funded by the National Natural Science Foundation(51202284);the Suzhou City Project(SYG201301);Jiangsu Project(BE2016083);State Key Laboratory of Functional Materials for Informatics,Shanghai Institute of Microsystem and Information Technology,Chinese Academy of Sciences;Key Laboratory of Nanodevices and Applications,Suzhou Institute of Nano-Tech and Nano-Bionics,Chinese Academy of Sciences

摘　　要：本文主要介绍了通过步进式光刻、反相剥离和F基等离子体刻蚀工艺在晶元级Si衬底上制备SiO_2图形的过程,在6 in(15.24 cm)Si衬底上实现了均匀的周期分别为1.0μm和1.6μm、深宽比分别为2.3和1.4的SiO_2周期性掩膜.尤其在周期为1μm的条件下,窗口通过过曝光和反相剥离工艺减小到330 nm,该尺寸超越了试验用步进式光刻设备的极限精度尺寸.在通过HF和KOH溶液处理后,得到了带有V型槽和较光滑侧壁的SiO图形的Si衬底,该图形适用于Ⅲ-Ⅴ半导体通过深宽比位错捕获技术的材料生长.这种均匀的晶元级图案制备方案促进了图形化Si衬底技术和Si基Ⅲ-Ⅴ半导体异质外延.In this paper, the fabrication of SiOz patterned Si substrate by stepper lithography, lift-off process and F-based plasma etching was demonstrated, by which the SiO2 trenches with periods of 1.0 μm and 1.6 μm and aspect ratios of 2.3 and 1.4 were uniformly formed on a 6 in（ 15.24 era） Si sub- strate. Especially, the opening window for the pattern with period of 1.0 μm was shortened to 330 nm by over-exposure and A1 film lift-off, which was beyond the limit of the stepper lithography used in the ex- periment. After further treatment by HF and KOH solutions, the smooth high-aspect-ratio SiO2 trenches were uniformly formed on V-grooved Si substrate, which makes the substrate suitable for the m-v semi- conductor through aspect-ratio-trapping technology. Such wafer-sealed uniform fabrication technology can promote the development of patterned Si substrates and Ⅲ-V semiconductor hetero-epitaxy on them.

关 键 词：图形衬底 异质外延 高深宽比 

分 类 号：TN304.2[电子电信—物理电子学]