云南高校图书馆联盟文献共享服务平台- 国家自然科学基金(s61234002)

检索规则说明：AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：范例一： (K=图书馆学 OR K=情报学) AND A=范并思　　　　范例二：J=计算机应用与软件 AND (U=C++ OR U=Basic) NOT M=Visual

全部期刊核心期刊 EI来源期刊 SCI来源期刊 CA来源期刊 CSCD来源期刊 CSSCI来源期刊

A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application被引量：2: 《Journal of Semiconductors》2017年第7期56-63,共8页Hao Zheng Zhangming Zhu Rui Ma; supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044); This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of ...; 关键词：class D amplifier filterless THD feedback loop PWM

A 10 b 50 MS/s two-stage pipelined SAR ADC in 180 nm CMOS被引量：1: 《Journal of Semiconductors》2016年第6期136-140,共5页沈易刘术彬朱樟明; supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033);the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory(No.ZHD201302); A 10-bit 50 MS/s pipelined SAR ADC is presented which pipelines a 5-bit SAR-based MDAC with a 6-bit SAR ADC.The 1-bit redundancy relaxes the requirement for the sub-ADC decision in accuracy.The SAR-based and ＂half-g...; 关键词：ADC pipeline SAR MDAC

A 14-bit 40-MHz analog front end for CCD application: 《Journal of Semiconductors》2016年第6期141-151,共11页王静宇朱樟明刘术彬; supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033);the National High-Tech Program of China (No. 2013AA014103);the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302); A 14-bit,40-MHz analog front end（AFE） for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier（VGA） with nearly 42 dB gain range,a correlat...; 关键词：analog front end correlated double sampler variable gain amplifier ADC programmable clock

A 0.1–1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process被引量：1: 《Journal of Semiconductors》2016年第5期90-96,共7页钟波朱樟明; Project supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033);the National High-Tech Program of China(No.2013AA014103); A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is signif...; 关键词：phase lock loop freqency synthesizer dual path charge pump CMOS

An ultra-low-voltage rectifier for PE energy harvesting applications被引量：2: 《Journal of Semiconductors》2016年第2期126-130,共5页王静敏杨正朱樟明杨银堂; supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033);the National High-Tech Program of China(No.2013AA014103); An ultra low voltage rectifier with high power conversion efficiency （PCE） for PE energy harvesting ap- plications is presented in this paper. This is achieved by utilizing the DTMOS which the body terminal is conne...; 关键词：PE energy harvesting DTMOS input powered active rectifier

PMGA and its application in area and power optimization for ternary FPRM circuit被引量：2: 《Journal of Semiconductors》2016年第1期126-130,共5页汪鹏君厉康平张会红; supported by the Natural Science Foundation of Zhejiang Province(No.LY13F040003);the National Natural Science Foundation of China(Nos.61234002,61306041);the K.C.Wong Magna Fund in Ningbo University; Based on the research of population migration algorithms （PMAs）, a population migration genetic algo- rithm （PMGA） is proposed, combining a PMA with a genetic algorithm. A scheme of area and power optimization for...; 关键词：PMGA temary FPRM circuit area and power optimization polarity search

Modeling of channel mismatch in time-interleaved SAR ADC: 《Journal of Semiconductors》2015年第9期136-142,共7页李登全张靓朱樟明杨银堂; Project supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033);the National High-Tech Program of China(No.2013AA014103); In a time-interleaved analog-to-digital converter （TI ADC）, several individual ADCs operate in parallel to achieve a higher sampling rate. Low power consumption as well as good linearity can be obtained by applying ...; 关键词：analog-to-digital converter time interleaved successive approximation register channel mismatch

An energy-efficient and highly linear switching capacitor procedure for SAR ADCs: 《Journal of Semiconductors》2015年第5期175-180,共6页马瑞白文彬朱樟明; Project supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033);the National High-Tech Program of China(Nos.2012AA012302,2013AA014103); An energy-efficient and highly linear capacitor switching procedure for successive approximation regis- ter （SAR） ADCs is presented. The proposed switching procedure achieves 37% less switching energy when compared ...; 关键词：analog-to-digital converter capacitor switching procedure switching energy LINEARITY successive approximation register

A high efficiency and power factor, segmented linear constant current LED driver被引量：1: 《Journal of Semiconductors》2015年第4期165-171,共7页励勇远过伟朱樟明; supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033); A high efficiency, high power factor, and linear constant current LED driver based on adaptive seg- mented linear architecture is presented. When the input voltage varied, the proposed LED driver automatically switche...; 关键词：high efficiency high power factor SEGMENTED linear constant LED driver

A high speed low power low offset dynamic comparator used in SHA-less pipelined ADC: 《Journal of Semiconductors》2014年第5期110-117,共8页刘术彬朱樟明杨银堂刘帘曦; supported by the National Natural Science Foundation of China(Nos.61234002,61006028);the National High-Tech Program of China(Nos.2012AA012302,2013AA014103);the PhD Programs Foundation of Ministry of Education of China(No.20120203110017); A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital ...; 关键词：SHA-less ADC dynamic comparator high speed low offset low power transmission gate

国家自然科学基金(s61234002)