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Design of 25 Gbit/s half-rate CDR with 1:2 demultiplexer for 100 GbE optical interconnects: 《The Journal of China Universities of Posts and Telecommunications》2015年第2期96-100,共5页Hu Zhengfei Chen Yingmei Yao Jianguo Xue Shaojia; supported by the Communication Systems Project of Jiangsu Department (JHB04010);the National Natural Science Foundation of China (60976029); A 25 Gbit/s clock and data recovery （CDR） circuit with 1：2 demultiplexer for 100 Gbit/s Ethemet （100 GbE） optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company （TSMC...; 关键词：CDR bang-bang phase detector quadrature voltage-controlled oscillator （QVCO） 100 GbE

Verilog HDL modeling and design of 10Gb/s SerDes full rate CDR in 65nm CMOS: 《High Technology Letters》2014年第2期140-145,共6页陈莹梅 Chen Xuehui Yi Lvfan Wen Guanguo; Supported by the National High Technology Research and Development Programme of China(No.2011AA010301);the Research Foundation of Zhongxing Telecom Equipment Corporation and the National Natural Science Foundation of China(No.60976029); Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behav...; 关键词：VERILOG-HDL behavioral level model （ BLM） phase locked loops （ PLL） clock and data recovery （CDR）

Design of 15 Gb/s inductorless limiting amplifier with RSSI and LOS indication in 65nm CMOS: 《High Technology Letters》2014年第1期92-96,共5页陈莹梅 Xu Zhigang Wang Tao Zhang Li; Supported by the National High Technology Research and Development Programme of China(No.2011AA010301);the National Natural Science Foundation of China(No.60976029); A limiting amplifier IC implemented in 65nm CMOS technology and intended for high-speed op- tical fiber communications is described in this paper. The inductorless limiting amplifier incorporates 5-stage 8 dB gain lim...; 关键词：limiting amplifier receiver signal strength indictor （RSSI） loss of signal（LOS） full-wave rectifier third order active feedback

Low power 13 Gbit/s VCSEL current driver in 0.18 μm CMOS for optical interconnection: 《The Journal of China Universities of Posts and Telecommunications》2013年第2期125-128,共4页CHEN Ying-mei WANG Jin-fei ZHANG Li LI Wei; supported by the Hi-Tech Research and Development Program of China(2011AA010301);the National Natural Science Foundation of China(60976029); A design of 13 Gbit/s vertical cavity surface emitting laser （VCSEL） driver using 0.18 μm complementary metal oxide semiconductor （CMOS） technology is presented in this paper. The core unit of the driver consists...; 关键词：VCSEL CMOS laser current driver active feedback

4-channel,40 Gb/s front-end amplifier for parallel optical receiver in 0.18 μm CMOS被引量：2: 《Science China(Information Sciences)》2013年第4期162-168,共7页CHEN YingMei ZHU Lei ZHANG Li LI Wei; supported by National High-tech R&D Program of China (863 Program) (Grant No. 2011AA010301);National Natural Science Foundation of China (Grant No. 60976029); This paper proposed a 4-channel parallel 40 Gb/s front-end amplifier （FEA） in optical receiver for parallel optical transmission system. A novel enhancement type regulated cascade （ETRGC） configuration with an act...; 关键词：enhancement type regulated cascade （ETRGC） active inductor transimpedance amplifier limiting amplifier three-order interleaving active feedback

Design of 10 GHz eight-phase voltage controlled oscillator in 90nm CMOS: 《The Journal of China Universities of Posts and Telecommunications》2012年第6期113-117,共5页CHEN Ying-mei WANG Hui YAN Shuang-chao ZHANG Li LI Wei; supported by the National High Technology Research and Development Program of China(2011AA010301);the National Natural Science Foundation of China(60976029); A novel 10 GHz eight-phase voltage-controlled oscillator （VCO） architecture applied in clock and data recovery （CDR） circuit for 40 Gbit/s optical communications system is proposed. Compared with the traditional e...; 关键词：VCO eight-phase LC ring oscillator CL ladder filtering

A 10 GHz multiphase LC VCO with a ring capacitive coupling structure被引量：6: 《Science China(Information Sciences)》2012年第11期2656-2662,共7页CHEN YingMei WANG Hui YAN ShuangChao ZHANG Li; supported by National Natural Science Foundation of China (Grant No. 60976029);National High Technology Research and Development Program of China (Grant No. 2011AA010301); A multiphase LC voltage-controlled oscillator （VCO） with a novel capacitive coupling CL ladder filter structure is proposed in this paper and this 10 GHz eight-phase VCO is applied in clock and data recovery （CDR）...; 关键词：voltage controlled oscillator （VCO） clock and data recovery （CDR） eight-phase capacitive cou-pling CL ladder filtering

A 40 Gbit/s fully integrated optical receiver analog front-end in 90 nm CMOS被引量：2: 《The Journal of China Universities of Posts and Telecommunications》2012年第1期124-128,共5页XU Zhi-gang CHEN Ying-mei WANG Tao CHEN Xue-hui ZHANG Li; supported by the National Natural Science Foundation of China (60976029); A fully integrated 40 Gbit/s optical receiver analog front-end （AFE） including a transimpedance amplifier （TIA） and a limiting amplifier （LA） for short distance communication is described in this paper. The prop...; 关键词：optical receiver transimpedance amplifier limiting amplifier active feedback negative capacitance inductor peaking

Jitter analysis and modeling of a 10 Gbit/s SerDes CDR and jitter attenuation PLL被引量：2: 《The Journal of China Universities of Posts and Telecommunications》2011年第6期122-126,共5页WANG Hui CHEN Ying-mei YI Lv-fan WEN Guan-guo; supported by the National Natural Science Foundation of China (60976029);the Research Foundation of Zhongxing Telecom Equipment Corporation; Jitter analysis and a linear model is proposed in this paper which predicts the characteristics of serial-deserial （SerDes） clock and data recovery circuit, and the characteristics include jitter transfer, jitter to...; 关键词：OTN SERDES JITTER CDR PLL

A low-jitter low-power monolithically integrated optical receiver for SDH STM-16被引量：2: 《Science China(Information Sciences)》2011年第6期1293-1299,共7页CHEN YingMei WANG ZhiGong & ZHANG Li; supported by the National Natural Science Foundation of China(Grant No.60976029); A high-scale integrated optical receiver including a preamplifier, a limiting amplfiaer, a clock anO data recovery （CDR） block, and a 1：4 demultiplexer （DEMUX） has been realized in a 0.25 p,m CMOS technology. Usi...; 关键词：optical receiver JITTER PREAMPLIFIER limiting amplifier clock and data recovery DEMULTIPLEXER

国家自然科学基金(60976029)