Pixel-parallel PE and SIMD architectures are widely used in high-speed image processing to enhance computing power. With fully exploiting the data level parallelism of low- and middle-level image processing, SIMD arch...
supported by the National Natural Science Foundation of China (Grants Nos. 60703072, 60673167);the Funds for Creative Research Groups of China (Grants No. 60621003);the National Basic Research Programof China (Grant No. 2005CB321801)
Building distributed applications is difficult mostly because of concurrency management. Existing approaches primarily include events and threads. Researchers and developers have been debating for decades to prove whi...
Under the direction of design space theory,in this paper we discuss the design of a superscalar pipelining using the way of multiple issues,and the implement of a superscalar based RISC DSP architecture,SDSP.Furthermo...
The performance of scalable shared-memory multiprocessors suffers from three types of latency; memory latency, the latency caused by inter-process synchronization ,and the latency caused by instructions that take mult...
Tomasulo algorithm, a dynamic scheduling technique designed for float point unit(FPU) to exploit instruction level parallelism for single thread only is improved into T Tomasulo algorithm to support multiple parallel...