Project supported by the National Natural Science Foundation of China(No.61376032)
A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate volt...
Project supported by the National Natural Science Foundation of China(Nos.61006027,61176030);the Research Foundation of Key Laboratory of Analog Integrated Circuit(Nos.9140C0902120C09034,9140c090204130c09042);the Fundamental Research Funds for the Central Universities of China(No.ZYGX2012J003)
A 2.5 GS/s 14-bit D/A converter(DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a "5+9"segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger out...
Project supported by National Basic Research Program of China(No.2010CB327400);the Natural Science Foundation of Shandong Province,China(No.ZR2013FL007)
A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is pre- sented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold ampli- ...
Project supported by the National Natural Science Foundation of China(No.61271331);the Jiangsu Provincial PAPD Program
A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compro...
Project supported by the National High Technology Research and Development Program of China(No.2009AA011605);the National Natural Science Foundation of China(No.61076027)
A programmable 14-bit 1-GS/s current-steering digital-to-analog converter is presented. It features a selectable interpolation rate (2x/4x/8x) with a programmable interpolation filter. To improve the high-frequency ...
supported by the Microelectronics Laboratory,Department of Science and Electronics,Beijing Institute of Technology,and the Photonics Laboratory,Department of Electrical Engineering,University of California-Los Angeles
We report a high-speed flash analog to digital converter(ADC) linearization technique employing the inverse Volterra model and digital post processing.First,a 1.25 GS/s 5-bit flash ADC is designed using a 0.18μm CM...
We have studied the influence of hot-carrier degradation effects on the drain current of a gate-stack double-gate (GS DG) MOSFET device. Our analysis is carried out by using an accurate continuous current-voltage (...
Project supported by the National High Technology Research and Development Program of China(No.2009AA01Z261);the State Key Laboratory of Wireless Telecommunication,Southeast University
A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier(THA) in 0.13μm CMOS for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The challenge is in implementing a sub-samplin...
A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μm CMOS.The calibration method based on DAC trimming improves the linearity and dynamic perfo...
A CMOS voltage reference, which is based on VGs and/x ΔGS in the weak inversion region, has been designed and implemented in standard 0.6μm CMOS technology. No diodes and parasitic bipolar junction transistors (BJT...