多晶硅晶粒间界的线性陷阱模型  

Linear Trapping Model of Polysilicon Grain-boundary

作　　者：赵杰[1] 张安康 魏同立 孙勤生[1] 

机构地区：[1]东南大学微电子中心,南京大学

出　　处：《固体电子学研究与进展》1996年第4期336-343,共8页Research & Progress of SSE

摘　　要：采用深能级瞬态谱仪（ＤＬＴＳ）测试多晶硅ｎ＋ｐ二极管势垒区深能级谱。利用ＤＬＴＳ实验结果，对Ｇ．Ｂａｃｃａｒｉｎａ等提出的均匀陷阱模型进行修正，提出多晶硅晶粒间界的线性陷阱模型。运用该修正模型，可采用迭代法求得多晶硅电学参数──势垒高度Ｅｂ、电导率激活能Ｅａ与多晶硅掺杂浓度Ｎｃ间关系。计算结果表明，多晶硅晶粒间界的线性陷阱模型具有理论合理性。In this paper, the deep level transient spectrums of polysilicon n+pdiode depletion region have been measured by use of DLTS instrument. According to the DLTS experimental results, the uniform trapping model set by G. Baccarinaetc. has been modified and the linear trapping moael of the grain-boundary has been proposed. Using the modified model, the relationship between the polysilicon electrical parameters, barrier height Eb as well as activation energy Ea, and the dopping level NG can be solved iteratively. The calculation results show that the linear trapping model of the grain-boundary is possessed of theoretical reasonableness.

关 键 词：深能级瞬态谱 线性陷阱模型 晶粒间界 多晶硅 

分 类 号：O471.5[理学—半导体物理] TN304.12[理学—物理]