PIPELINE_ADC

作品数：18被引量：13H指数：2
导出分析报告
相关作者：陈超李斌桥姚素英朱天成吴毅强更多>>
相关机构：电子科技大学东南大学哈尔滨工业大学天津大学更多>>
相关期刊：《辽宁大学学报（自然科学版）》《微电子学》《山东大学学报（工学版）》《现代电子技术》更多>>
相关基金：国家自然科学基金国家高技术研究发展计划上海市科学技术委员会资助项目上海-AM基金更多>>
-
在结果中检索

检索结果分析

结果分析中...
选择条件：
  • 期刊=Journal of Semiconductorsx
共 条 记 录，以下是1-9
全选清除导出
参考文献引证文献引用追踪
视图：
排序：
A 10 bit 200 MS/s pipeline ADC using loading-balanced architecture in 0.18 μm CMOS被引量：2
《Journal of Semiconductors》2017年第7期103-110,共8页Linfeng Wang Qiao Meng Hao Zhi Fei Li 
A new loading-balanced architecture for high speed and low power consumption pipeline analog-todigital converter（ADC） is presented in this paper. The proposed ADC uses SHA-less, op-amp and capacitor-sharing techniqu...
关键词：pipeline ADC loading-balanced op-amp sharing SHA-Less MDAC scaling down 
A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC
《Journal of Semiconductors》2014年第5期118-123,共6页岳森 赵毅强 庞瑞龙 盛云 
supported by the National Science and Technology Major Project of China(No.2012ZX03004008)
A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differe...
关键词：sample/hold circuit pipeline ADC gain-boosted OTA bootstrapped switch 
A 1.2 V dual-channel 10 bit pipeline ADC in 55 nm CMOS for WLAN receivers
《Journal of Semiconductors》2013年第9期112-116,共5页龚正 胡雪青 颜峻 石寅 
A power-efficient technique for pipeline analog-to-digital converters （ADCs） is proposed. By sharing amplifiers between 1/Q channels, the power dissipation of the ADCs is reduced by almost one-half compared to conve...
关键词：ADC amplifier sharing I/Q amplifier sharing WLAN receiver reference buffer 
A digital background calibration algorithm of a pipeline ADC based on output code calculation
《Journal of Semiconductors》2012年第11期110-114,共5页邵健健 李玮韬 孙操 李福乐 张春 王志华 
This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter（ADC）.The algorithm does not modify the analog circuit of pipelined stages and cal...
关键词：pipeline ADC output code calculation background calibration 
A novel low-offset dynamic comparator for sub-1-V pipeline ADCs被引量：1
《Journal of Semiconductors》2011年第8期93-97,共5页杨金达 王贤彪 李立 程旭 郭亚炜 曾晓洋 
Project supported by the National High Technology Research and Development Program of China(No.2009AA011600);the Young Scientists Fund of Fudan University,China(No.09FQ33);the State Key Laboratory of ASIC and System,Fudan University,China(No. 09MS008)
A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters （ADCs） has been proposed.In the proposed comparator,a CMOS switch takes the place of the dynamic current sources in the d...
关键词：COMPARATOR high speed low voltage low offset ADC 
A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer
《Journal of Semiconductors》2011年第1期90-96,共7页陈奇辉 秦亚杰 陆波 洪志良 
Project supported by the National High Technology Research and Development Program of China(No.2009AA011607);the State Key Laboratory of China
A 12-bit 30 MSPS pipeline analog-to-digital converter （ADC） implemented in 0.13μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the...
关键词：analog-to-digital converter pipeline SHA removing OPAMP on-chip reference buffer 
A low power 12-b 40-MS/s pipeline ADC
《Journal of Semiconductors》2010年第3期95-100,共6页殷秀梅 魏琦 许莱 杨华中 
supported by the National Natural Science Foundation of China(No.60976032).
This paper describes a 12-bit, 40-MS/s pipelined A/D converter （ADC） which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational tra...
关键词：analog-to-digital converter A/D converter PIPELINE telescope OTA low power high linearity 
A 10bit 50MS/s Pipeline ADC Design for a Million Pixels Level CMOS Image Sensor被引量：3
《Journal of Semiconductors》2008年第10期1939-1946,共8页朱天成 姚素英 袁小星 李斌桥 
国家自然科学基金(批准号:60576025);天津市自然科学基金重点项目(批准号:07JCZDJC10400)资助~~
Noise and mismatch are important error sources in pipeline ADCs,so careful calculation and system simulation are carried out using Matlab software. To reduce power consumption while not lose performance, the amplifier...
关键词：pipeline ADC CMOS image sensor noise and mismatch suppress low power consumption design 
A Low-Power-Consumption 9bit 10MS/s Pipeline ADC for CMOS Image Sensors被引量：1
《Journal of Semiconductors》2007年第12期1924-1929,共6页朱天成 姚素英 李斌桥 
国家自然科学基金资助项目(批准号:60576025)~~
A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifier...
关键词：pipeline ADC low power design CMOS image sensor large signal processing range 
全选清除导出
共1页<1>
检索报告 对象比较 聚类工具 使用帮助 返回顶部