An algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented.Given a two-terminal net,the algorithm can minimize the total number of buffers inserted to meet ...
An algorithm is presented for better legal solution in detailed placement of large scale mixed macros and standard cells IC design.Due to the limitation of computing complexity,an effective and efficient initial place...
A global routing algorithm with performance optimization under multi constraints is proposed,which studies RLC coupling noise,timing performance,and routability simultaneously at global routing level.The algorithm is...
An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate dela...
An algorithm to resolve the coupling effect problem is proposed during the cross point assignment (CPA) stage.In the algorithm,the priority queue concept and the rip-up and reroute strategy are combined to control cro...
As develops in deep sub micron designs,the interconnect crosstalk becomes much more serious.Espe cially, the coupling inductance can not be ignored in gigahertz designs.So shield insertion is an efficient techniq...