国家高技术研究发展计划(2011AA10305)

作品数：9被引量：12H指数：2
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相关作者：潘敏冯军李竹王志功杨格亮更多>>
相关机构：东南大学合肥工业大学更多>>
相关期刊：《电子学报》《High Technology Letters》《东南大学学报（自然科学版）》《红外与毫米波学报》更多>>
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A 10Gb/s combined equalizer in 0.18μm CMOS technology for backplane communication
《High Technology Letters》2015年第2期205-211,共7页张明科 Hu Qingsheng 
Supported by the National High Technology Research and Development Programme of China(No.2011AA10305)
This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure t...
关键词：analog equalizer decision feedback equalizer （DFE） inductive peaking current mode logic （CML） 
A 3.16–7 GHz transformer-based dual-band CMOS VCO
《Journal of Semiconductors》2015年第3期106-113,共8页李竹 王志功 李智群 李芹 刘法恩 
Project supported by the National High Technology Research and Development Program of China(No.2011AA10305);the National Natural Science Foundation of China(No.60901012)
A dual-band, wide tuning range voltage-controlled oscillator that uses transformer-based fourth-order（LC） resonator with a compact common-centric layout is presented. Compared with the traditional wide band（VCO）, ...
关键词：CMOS phase noise voltage-controlled oscillator （VCO） WIDEBAND transformer 
IC design of low power, wide tuning range VCO in 90 nm CMOS technology被引量：1
《Journal of Semiconductors》2014年第12期133-138,共6页李竹 王志功 李智群 李芹 刘法恩 
supported by the National Basic Research Program of China(No.2010CB327404);the National High Technology Research and Development Program of China(No.2011AA10305);the National Natural Science Foundation of China(No.60901012)
A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductanc...
关键词：CMOS MICROWAVE millimeter wave IMOS varactor phase noise voltage controlled oscillators 
CMOS毫米波低功耗超宽带共栅低噪声放大器（英文）被引量：4
《红外与毫米波学报》2014年第6期584-590,共7页杨格亮 王志功 李智群 李芹 刘法恩 李竹 
Supported by the 973 project(2010CB327404);the 863 project(2011AA10305);National Natural Science Foundation of China(61106024,60901012)
陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器（LNA）.该LNA用标准90-nm RFCMOS工艺实现并具有如下特征：在28.5～39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27～42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最...
关键词：毫米波 宽带 互补金属氧化物半导体(CMOS) 共栅 低噪声放大器(LNA) 集成电路(IC) 
Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop被引量：1
《Journal of Semiconductors》2014年第10期119-125,共7页刘法恩 王志功 李智群 李芹 陈胜 
Project supported by the National Basic Research Program of China(No.2010CB327404);the National High Technology Research and Development Program(No.2011AA10305);the National Natural Science Foundation of China(No.60901012)
Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eli...
关键词：CMOS phase-frequency detector charge-pump current compensation accelerating acquisition PLL 
A 14.5Gb/s word alignment circuit in 0.18μm CMOS technology for high-speed SerDes
《High Technology Letters》2014年第3期328-332,共5页阮伟华 Hu Qingsheng 
Supported by the National High Technology Research and Development Programme of China(No.2011AA10305)
This paper presents a word alignment circuit for high speed SerDes system.By using pipeline structure and circuit optimization techniques,the speed of the aligner is increased,and its performance is improved further t...
关键词：comma detection word alignment PIPELINE full custom parallel structure 
12.5Gb/s 0.18μm CMOS时钟与数据恢复电路设计被引量：3
《电子学报》2014年第8期1630-1635,共6页潘敏 冯军 杨婧 杨林成 
国家863高技术研究发展计划(No.2011AA10305)
采用0.18μm CMOS工艺设计实现了一个12.5 Gb/s半速率时钟数据恢复电路(CDR)以及1:2分接器,该CDR及分接器是串行器/解串器(SerDes)接收机中的关键模块,为接收机系统提供6.25GHz的时钟及经二分接后速率降半的6.25Gb/s数据.该电路包括Bang...
关键词：串行器/解串器(SerDes) 时钟数据恢复电路(CDR) 鉴频鉴相器(PFD) 压控振荡器(VCO) 
低功耗0.18μm 10Gbit/s CMOS 1∶4分接器设计被引量：2
《东南大学学报（自然科学版）》2013年第2期274-278,共5页潘敏 冯军 
国家高技术研究发展计划(863计划)资助项目(2011AA10305);国家国际科技合作资助项目(2011DFA11310)
为了实现光纤通信系统中高速分接器低功耗的需求,采用0.18μm CMOS工艺实现了一个全CMOS逻辑10 Gbit/s 1∶4分接器.整个系统采用半速率树型结构,由1∶2分接单元、2分频器单元以及缓冲构成,其中锁存器单元均采用动态CMOS逻辑电路,缓冲由...
关键词：分接器 低功耗 动态CMOS逻辑 
A 31.7-GHz high linearity millimeter-wave CMOS LNA using an ultra-wideband input matching technique被引量：1
《Journal of Semiconductors》2012年第12期112-117,共6页杨格亮 王志功 李智群 李芹 李竹 刘法恩 
Project supported by the National Basic Research Program of China(No.2010CB327404);the National High Technology Research and Development Program of China(No.2011AA10305);the International Cooperation Projects in Science and Technology,China(No. 2011DFA11310)
A CMOS low-noise amplifier （LNA） operating at 31.7 GHz with a low input return loss （S11） and high linearity is proposed. The wideband input matching was achieved by employing a simple LC compounded network to gen...
关键词：CMOS low noise amplifier input matching MILLIMETER-WAVE 
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