Project supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028);the National High-Tech R&D Program of China(No.2009AA01 Z258);the Shaanxi Special Major Technological Innovation Program(No.2009ZKC02-11)
A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop (DLL), and a new differential structure is used to improve the precisio...
supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028,61006028);the National High-Tech R&D Program of China(No.2009AA01Z258);the Shaanxi Special Major Technological Innovation Program(No. 2009ZKC02-11 )
A new design technique for merging the front-end sample-and-hold amplifier(SHA) into the first multiplying digital-to-analog converter(MDAC) is presented.For reducing the aperture error in the first stage of the p...
supported by the National Natural Science Foundation of China (Grant Nos.60725415 and 60971066)
According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed r...
Project supported by the National Natural science Foundation of China(Nos.60725415,60971066)
An offset cancellation technique for a SAR (successive approximation register) ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and...
supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028);the National High-Tech Research and Development Program of China(No.2009AA01Z258);the National Science & Technology Important Project of China (No.2009ZX01034-002001-005)
This paper presents a 10-bit 100-MSample/s analog-to-digital (A/D) converter with pipelined folding architecture. The linearity is improved by using an offset cancellation technique and a resistive averaging interpo...
Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415, 60971066, and 61006028);the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260);the National Key Lab Foundation,China (Grant No. ZHD200904)
On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising cloc...
Project supported by the National Natural Science Foundation of China(Grant Nos.60725415 and 60971066);the National Science&Technology Important Project of China(Grant No.2009ZX01034-002-001-005);The National Key Laboratory Foundation(Grant No.ZHD200904)
As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polyn...
Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066);the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260);the National Science & Technology Important Project of China (Grant No. 2009ZX01034-002-001-005)
Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swi...