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A clock generator for a high-speed high-resolution pipelined A/D converter被引量：1: 《Journal of Semiconductors》2013年第2期72-77,共6页赵磊杨银堂朱樟明刘帘羲; Project supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028);the National High-Tech R&D Program of China(No.2009AA01 Z258);the Shaanxi Special Major Technological Innovation Program(No.2009ZKC02-11); A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop （DLL）, and a new differential structure is used to improve the precisio...; 关键词：duty cycle stabilizer clock jitter dynamic logic non-overlap clock

An RLC interconnect analyzable crosstalk model considering self-heating effect: 《Chinese Physics B》2012年第2期552-560,共9页Zhu Zhang-Ming Liu Shu-Bin; supported by the National Natural Science Foundation of China (Grant Nos.60725415 and 60971066); According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed r...; 关键词：multilevel interconnects temperature distribution RLC crosstalk

SHA-less architecture with enhanced accuracy for pipelined ADC: 《Journal of Semiconductors》2012年第2期117-121,共5页Zhao Lei Yang Yintang Zhu Zhangming Liu Lianxi; supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028,61006028);the National High-Tech R&D Program of China(No.2009AA01Z258);the Shaanxi Special Major Technological Innovation Program(No. 2009ZKC02-11 ); A new design technique for merging the front-end sample-and-hold amplifier（SHA） into the first multiplying digital-to-analog converter（MDAC） is presented.For reducing the aperture error in the first stage of the p...; 关键词：pipelined analog-to-digital converter sample-and-hold amplifier SHA-less aperture error

An offset cancellation technique in a switched-capacitor comparator for SAR ADCs被引量：1: 《Journal of Semiconductors》2012年第1期144-148,共5页Tong Xingyuan Zhu Zhangming Yang Yintang; Project supported by the National Natural science Foundation of China(Nos.60725415,60971066); An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and...; 关键词：A/D converter switched-capacitor comparator PREAMPLIFIER regenerative latch low power low off-set

A 10-bit 100-MS/s CMOS pipelined folding A/D converter: 《Journal of Semiconductors》2011年第11期110-116,共7页李晓娟杨银堂朱樟明; supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028);the National High-Tech Research and Development Program of China(No.2009AA01Z258);the National Science & Technology Important Project of China (No.2009ZX01034-002001-005); This paper presents a 10-bit 100-MSample/s analog-to-digital （A/D） converter with pipelined folding architecture. The linearity is improved by using an offset cancellation technique and a resistive averaging interpo...; 关键词：analog-to-digital converter pipelined folding resistive averaging interpolation offset cancellation

Three-dimensional global interconnect based on a design window: 《Chinese Physics B》2011年第10期463-468,共6页钱利波朱樟明杨银堂; supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60676009);the Natural Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2009ZX01034-002-001-005); Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit （3D IC） is predicted exactly. Using the results of this model, a global interconnect desig...; 关键词：three-dimensional integrated circuit design window wiring resource bandwidth

A statistical RCL interconnect delay model taking account of process variations: 《Chinese Physics B》2011年第1期659-666,共8页朱樟明万达经杨银堂恩云飞; Project supported by the National Natural Science Foundation of China(Grant Nos.60725415 and 60971066);the National Science&Technology Important Project of China(Grant No.2009ZX01034-002-001-005);The National Key Laboratory Foundation(Grant No.ZHD200904); As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polyn...; 关键词：process variation interconnect line statistical delay successive linear approximation

A novel low-swing interconnect optimization model with delay and bandwidth constraints: 《Chinese Physics B》2010年第12期530-536,共7页朱樟明郝报田杨银堂李跃进; Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066);the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260);the National Science & Technology Important Project of China (Grant No. 2009ZX01034-002-001-005); Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swi...; 关键词：interconnect power repeater area low-swing circuit time delay BANDWIDTH

A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC被引量：3: 《Journal of Semiconductors》2010年第10期121-125,共5页佟星元杨银堂朱樟明盛文芳; Project supported by the National Natural Science Foundation of China(Nos.60725415,60971066,60676009,60776034,60803038);the National High-Tech Research and Development Program of China(Nos.2009AA01Z258,2009AA01Z260);the National Science & Technology Important Project of China(No.2009ZX01034-002-001-005); Based on a 5 MSBs （most-significant-bits）-plus-5 LSBs （least-significant-bits） C-R hybrid D/A conver sion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topol...; 关键词：analog-to-digital converter SAR touch screen SoC CMOS integrated circuits low power

A high precision high PSRR bandgap reference with thermal hysteresis protection被引量：3: 《Journal of Semiconductors》2010年第9期113-117,共5页杨银堂李娅妮朱樟明; supported by the National Natural Science Foundation of China(Nos.60725415,60971066);the National High-Tech Research and Development Program of China(Nos.2009AA01Z258,2009AA01Z260);the National Science & Technology Important Project of China(No.2009ZX01034-002-001-005); To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits,a high-order curvature-compensated bandgap voltage reference is presented employing...; 关键词：bandgap voltage reference curvature-compensated power supply rejection ratio over-temperature protection BCD process

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