supported by the State Key Development Program for Basic Research of China (No. 2005CB321600);the National High Technol-ogy Development Research and Program of China (No. 2008AA110901);the National Natural Science Foundation of China (Nos.60801045, 60803029, 60673146, 60603049);the Beijing Natural Science Foundation (No. 4072024)
This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage. The receiver occupies 300×500 μm2. With the novel half rate period calibration clock data r...
A sub-mA phase-locked loop fabricated in a 65nm standard digital CMOS process is presented. The impact of process variation is largely removed by a novel open-loop calibration that is performed only during start-up bu...
the National Natural Science Foundation of China(Grant Nos.60673146,60703017,60736012 and 60603049);the National High Technology Development 863 Program of China(Grant Nos.2006AA010201 and 2007AA01Z114);the National Grand Fundamental Research 973 Program of China(Grant Nos.2005CB321601 and 2005CB321603);Beijing Natural Science Foundation(Grant No.4072024).
Although the design of many kinds of microprocessors has been under developing for several decades, the computer architecture R&D community lacks well documented lessons and experiences about design decisions in the ...
This paper describes the design of a low voltage differential signal (LVDS) transmitter and receiver with high speed and low power for CPU, LCD, FPGA, and other fast links. In the proposed transmitter, a stable refe...