Project supported by the National Science and Technology Project of the Ministry of Science and Technology of China(Grant No.2010ZX02201);the National Natural Science Foundation of China(Grant No.61176069);the National Defense Pre-Research of China(Grant No.51308020304)
A novel low specific on-resistance (Ron,sp) lateral double-diffused metal oxide semiconductor (LDMOS) with a buried improved super-junction (BISJ) layer is proposed. A super-junction layer is buried in the drift...
Project supported by the National Natural Science Foundation of China(No.61176069);the Program for New Century Excellent Talentsin University of Ministry of Education of China(No.NCET-11-0062);the China Postdoctoral Science Foundation(No.2012T50771)
A low specific on-resistance(R on;sp/ SOI NBL TLDMOS(silicon-on-insulator trench LDMOS with an N buried layer) is proposed. It has three features: a thin N buried layer(NBL) on the interface of the SOI layer/bur...
Projects supported by the National Natural Science Foundation of China(No.61176069);the Special Financial Gnants from the China Postdoctoral Science Foundation and Chongqing(Nos.2012T50771,XM2012004)
An improved breakdown voltage (BV) SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenc...
supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2010ZX02201);the National Natural Science Foundation of China(No.61176069);the National Defense Pre-Research of China(No.51308020304)
A novel buffer super-junction (S J) lateral double-diffused MOSFET (LDMOS) with an N-type buried layer (NB) is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the...
Project supported by the National Natural Science Foundation of China(Grant No.61176069);the Program for New Century Excellent Talents in University of Ministry of Education of China(Grant No.NCET-11-0062);Project of 51308020304
A new silicon-on-insulator (SOI) power lateral MOSFET with a dual vertical field plate (VFP) in the oxide trench is proposed. The dual VFP modulates the distribution of the electric field in the drift region, whic...
supported by the National Natural Science Foundation of China(Nos.60976060,61176069);the National Key Laboratory of Analogue Integrated Circuit,China(No.9140C090304110C0905)
An analytical model for a novel high voltage silicon-on-insulator device with composite-k (relative per mittivity) dielectric buried layer (CK SOl) is proposed. In this structure, the composite-k buried layer is c...
supported by the National Natural Science Foundation of China (Grant No. 61176069);the State Key Laboratory Science Fund of Electronic Thin Films and Integrated Devices of China (Grant No. CXJJ201004);the National Key Laboratory Science Fund of Analog Integrated Circuit,China (Grant No. 9140C090304110C0905)
A novel low specific on-resistance (Ron,sp) silicon-on-insulator (SO1) p-channel lateral double-diffused metal-oxide semiconductor (pLDMOS) compatible with high voltage (HV) n-channel LDMOS (nLDMOS) is propo...
supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2010ZX02201);the National Natural Science Foundation of China (Grant No. 61176069);the National Defense Pre-Research of China (Grant No. 51308020304)
A novel super-junction lateral double-diffused metal-oxide semiconductor (SJ-LDMOS) with a partial lightly doped P pillar (PD) is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge...
Project supported by the National Natural Science Foundation of China (Grant No. 61176069);the National Key Laboratory of Analog Integrated Circuit,China (Grant No. 9140C090304110C0905);the Innovation Foundation of the State Key Laboratory of Electronic Thin Films and Integrated Devices,China (Grant No. CXJJ201004)
A new high voltage trench lateral double-diffused metal–oxide semiconductor (LDMOS) with ultra-low specific onresistance (R on,sp ) is proposed. The structure features a dual gate (DG LDMOS): a planar gate and...